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When the allocator rewrite a spill register with new virtual register, it replaces other operands of the same register. Watch out for situations where

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only some of the operands are sub-register uses.

llvm-svn: 43776
This commit is contained in:
Evan Cheng 2007-11-06 21:12:10 +00:00
parent 59b08debe3
commit c401482711
1 changed files with 12 additions and 3 deletions
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15
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -379,10 +379,19 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, unsigned reg) {
if (!MI->getOperand(j).isRegister())
continue;
unsigned RegJ = MI->getOperand(j).getReg();
if (RegJ != 0 && MRegisterInfo::isVirtualRegister(RegJ) &&
RegMap->isSubRegister(RegJ))
if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ))
continue;
bool isSubRegJ = RegMap->isSubRegister(RegJ);
if (isSubRegJ) {
assert(!isSubReg || RegMap->getSubRegisterIndex(RegJ) == SubIdx);
RegJ = RegMap->getSuperRegister(RegJ);
if (RegJ == li.reg) {
}
// Important to check "isSubRegJ == isSubReg".
// e.g. %reg1024 = MOVSX32rr16 %reg1025. It's possible that both
// registers are coalesced to the same register but only %reg1025 is
// a sub-register use. They should not be rewritten to the same
// register.
if (RegJ == li.reg && isSubRegJ == isSubReg) {
MI->getOperand(j).setReg(NewVReg);
HasUse |= MI->getOperand(j).isUse();
HasDef |= MI->getOperand(j).isDef();