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[Alignment][NFC] Transition to inferAlignFromPtrInfo

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Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: arsenm, jvesely, nhaehnle, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77120
This commit is contained in:
Guillaume Chatelet 2020-03-31 07:52:49 +00:00
parent d1b2c70fb7
commit c47c91f05a
6 changed files with 21 additions and 34 deletions
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6
include/llvm/CodeGen/GlobalISel/Utils.h
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@ -184,12 +184,6 @@ inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
/// FIXME: Remove once the transition to Align is over.
inline unsigned inferAlignmentFromPtrInfo(MachineFunction &MF,
const MachinePointerInfo &MPO) {
return inferAlignFromPtrInfo(MF, MPO).value();
}
/// Return the least common multiple type of \p Ty0 and \p Ty1, by changing
/// the number of vector elements or scalar bitwidth. The intent is a
/// G_MERGE_VALUES can be constructed from \p Ty0 elements, and unmerged into

8
lib/Target/AArch64/AArch64CallLowering.cpp
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@ -87,10 +87,9 @@ struct IncomingArgHandler : public CallLowering::ValueHandler {
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
Align);
inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}
@ -177,9 +176,8 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
.getReg(0);
}
MachineFunction &MF = MIRBuilder.getMF();
unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOStore, Size, Align);
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size,
inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildStore(ValVReg, Addr, *MMO);
}

24
lib/Target/AMDGPU/AMDGPUCallLowering.cpp
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@ -131,12 +131,11 @@ struct IncomingArgHandler : public CallLowering::ValueHandler {
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
// FIXME: Get alignment
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
Align);
inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}
@ -418,9 +417,8 @@ Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &B,
return B.buildPtrAdd(PtrType, KernArgSegmentVReg, OffsetReg).getReg(0);
}
void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B,
Type *ParamTy, uint64_t Offset,
unsigned Align,
void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, Type *ParamTy,
uint64_t Offset, Align Alignment,
Register DstReg) const {
MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
@ -429,11 +427,11 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B,
unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
Register PtrReg = lowerParameterPtr(B, ParamTy, Offset);
MachineMemOperand *MMO =
MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad |
MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant,
TypeSize, Align);
MachineMemOperand *MMO = MF.getMachineMemOperand(
PtrInfo,
MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
MachineMemOperand::MOInvariant,
TypeSize, Alignment);
B.buildLoad(DstReg, PtrReg, *MMO);
}
@ -508,7 +506,7 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
unsigned i = 0;
const unsigned KernArgBaseAlign = 16;
const Align KernArgBaseAlign(16);
const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F);
uint64_t ExplicitArgOffset = 0;
@ -529,9 +527,9 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
OrigArgRegs.size() == 1
? OrigArgRegs[0]
: MRI.createGenericVirtualRegister(getLLTForType(*ArgTy, DL));
unsigned Align = MinAlign(KernArgBaseAlign, ArgOffset);
Align Alignment = commonAlignment(KernArgBaseAlign, ArgOffset);
ArgOffset = alignTo(ArgOffset, DL.getABITypeAlignment(ArgTy));
lowerParameter(B, ArgTy, ArgOffset, Align, ArgReg);
lowerParameter(B, ArgTy, ArgOffset, Alignment, ArgReg);
if (OrigArgRegs.size() > 1)
unpackRegs(OrigArgRegs, ArgReg, ArgTy, B);
++i;

2
lib/Target/AMDGPU/AMDGPUCallLowering.h
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@ -27,7 +27,7 @@ class AMDGPUCallLowering: public CallLowering {
uint64_t Offset) const;
void lowerParameter(MachineIRBuilder &B, Type *ParamTy, uint64_t Offset,
unsigned Align, Register DstReg) const;
Align Alignment, Register DstReg) const;
/// A function of this type is used to perform value split action.
using SplitArgTy = std::function<void(ArrayRef<Register>, Register, LLT, LLT, int)>;

5
lib/Target/ARM/ARMCallLowering.cpp
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@ -323,10 +323,9 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {
MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
MachinePointerInfo &MPO) {
MachineFunction &MF = MIRBuilder.getMF();
unsigned Alignment = inferAlignmentFromPtrInfo(MF, MPO);
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad, Size, Alignment);
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
inferAlignFromPtrInfo(MF, MPO));
return MIRBuilder.buildLoad(Res, Addr, *MMO);
}

10
lib/Target/X86/X86CallLowering.cpp
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@ -148,11 +148,10 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
Register ExtReg = extendRegister(ValVReg, VA);
unsigned Alignment = inferAlignmentFromPtrInfo(MF, MPO);
auto MMO =
MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore,
VA.getLocVT().getStoreSize(), Align(Alignment));
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore,
VA.getLocVT().getStoreSize(),
inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildStore(ExtReg, Addr, *MMO);
}
@ -249,10 +248,9 @@ struct IncomingValueHandler : public CallLowering::ValueHandler {
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
Align);
inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}