RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
Code Issues Projects Releases Wiki Activity

Remove CRC32 instructions from AArch64InstrInfo::hasShiftedReg

Browse Source 
Summary:
A53 scheduler causes an assertion failure on all CRC instructions:
include/llvm/CodeGen/MachineInstr.h:280: const llvm::MachineOperand
&llvm::MachineInstr::getOperand(unsigned int) const: Assertion `i <
getNumOperands() && "getOperand() out of range!"' failed.

The case statements corresponding to CRC instructions are incorrect and should
be removed.

Also adding a testcase while on this.

Reviewers: t.p.northover, javed.absar, apazos, rengolin

Reviewed By: rengolin

Subscribers: evandro, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D30274

llvm-svn: 297582
This commit is contained in:
Azharuddin Mohammed 2017-03-12 14:02:32 +00:00
parent a762b2b26e
commit c515dddbb1
2 changed files with 1 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -1345,14 +1345,6 @@ bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) const {
case AArch64::BICSXrs:
case AArch64::BICWrs:
case AArch64::BICXrs:
case AArch64::CRC32Brr:
case AArch64::CRC32CBrr:
case AArch64::CRC32CHrr:
case AArch64::CRC32CWrr:
case AArch64::CRC32CXrr:
case AArch64::CRC32Hrr:
case AArch64::CRC32Wrr:
case AArch64::CRC32Xrr:
case AArch64::EONWrs:
case AArch64::EONXrs:
case AArch64::EORWrs:

1
test/CodeGen/AArch64/arm64-crc32.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -mtriple=arm64-eabi -mattr=+crc -o - %s | FileCheck %s
; RUN: llc -mtriple=arm64-eabi -mcpu=cortex-a53 -mattr=+crc -o - %s | FileCheck %s
define i32 @test_crc32b(i32 %cur, i8 %next) {
; CHECK-LABEL: test_crc32b: