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[AArch64][GlobalISel] Add isel support for a couple vector exts/truncs
Add support for - v4s16 <-> v4s32 - v2s64 <-> v2s32 And update tests that use them to show that we generate the correct instructions. Differential Revision: https://reviews.llvm.org/D57832 llvm-svn: 353732
This commit is contained in:
Jessica Paquette
parent
93c1e7153b
commit
c562e11af8
@ -274,9 +274,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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// FP conversions
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getActionDefinitionsBuilder(G_FPTRUNC).legalFor(
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{{s16, s32}, {s16, s64}, {s32, s64}});
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{{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}});
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getActionDefinitionsBuilder(G_FPEXT).legalFor(
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{{s32, s16}, {s64, s16}, {s64, s32}});
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{{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}});
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// Conversions
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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@ -67,6 +67,48 @@ body: |
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$s0 = COPY %1(s32)
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...
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---
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name: fptrunc_v4s16_v4s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FCVTNv4i16:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
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; CHECK: $d0 = COPY [[FCVTNv4i16]]
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%0(<4 x s32>) = COPY $q0
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%1(<4 x s16>) = G_FPTRUNC %0
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$d0 = COPY %1(<4 x s16>)
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...
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---
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name: fptrunc_v2s32_v2s64_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FCVTNv2i32:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
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; CHECK: $d0 = COPY [[FCVTNv2i32]]
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%0(<2 x s64>) = COPY $q0
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%1(<2 x s32>) = G_FPTRUNC %0
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$d0 = COPY %1(<2 x s32>)
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...
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---
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name: fpext_s32_s16_fpr
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legalized: true
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@ -133,6 +175,48 @@ body: |
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$d0 = COPY %1(s64)
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...
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---
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name: fpext_v4s32_v4s16_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FCVTLv4i16:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
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; CHECK: $q0 = COPY [[FCVTLv4i16]]
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%0(<4 x s16>) = COPY $d0
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%1(<4 x s32>) = G_FPEXT %0
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$q0 = COPY %1(<4 x s32>)
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...
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---
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name: fpext_v2s64_v2s32_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FCVTLv2i32:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
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; CHECK: $q0 = COPY [[FCVTLv2i32]]
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%0(<2 x s32>) = COPY $d0
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%1(<2 x s64>) = G_FPEXT %0
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$q0 = COPY %1(<2 x s64>)
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...
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---
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name: sitofp_s32_s32_fpr
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legalized: true
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@ -1,39 +1,61 @@
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -O0 -fast-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* \
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; RUN: -mtriple=arm64-eabi -aarch64-neon-syntax=apple \
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; RUN: | FileCheck %s --check-prefixes=GISEL,FALLBACK
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f64_f32)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f64_f32)
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define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_f64_f32:
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; GISEL-LABEL: test_vcvt_f64_f32:
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%vcvt1.i = fpext <2 x float> %x to <2 x double>
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; CHECK: fcvtl v0.2d, v0.2s
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; GISEL: fcvtl v0.2d, v0.2s
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ret <2 x double> %vcvt1.i
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; CHECK: ret
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; GISEL: ret
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}
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f64_f32)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f64_f32)
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define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %x) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_f64_f32:
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; GISEL-LABEL: test_vcvt_high_f64_f32:
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%cvt_in = shufflevector <4 x float> %x, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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%vcvt1.i = fpext <2 x float> %cvt_in to <2 x double>
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; CHECK: fcvtl2 v0.2d, v0.4s
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; GISEL: fcvtl2 v0.2d, v0.4s
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ret <2 x double> %vcvt1.i
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; CHECK: ret
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; GISEL: ret
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}
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_f32_f64)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_f32_f64)
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define <2 x float> @test_vcvt_f32_f64(<2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_f32_f64:
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; GISEL-LABEL: test_vcvt_f32_f64:
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%vcvt1.i = fptrunc <2 x double> %v to <2 x float>
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; CHECK: fcvtn
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; GISEL: fcvtn
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ret <2 x float> %vcvt1.i
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; CHECK: ret
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; GISEL: ret
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}
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; FALLBACK-NOT: remark{{.*}}G_FPEXT{{.*}}(in function: test_vcvt_high_f32_f64)
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; FALLBACK-NOT: remark{{.*}}fpext{{.*}}(in function: test_vcvt_high_f32_f64)
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define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) nounwind readnone ssp {
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; CHECK-LABEL: test_vcvt_high_f32_f64:
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; GISEL-LABEL: test_vcvt_high_f32_f64:
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%cvt = fptrunc <2 x double> %v to <2 x float>
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%vcvt2.i = shufflevector <2 x float> %x, <2 x float> %cvt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK: fcvtn2
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; GISEL: fcvtn2
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ret <4 x float> %vcvt2.i
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; CHECK: ret
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; GISEL: ret
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}
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define <2 x float> @test_vcvtx_f32_f64(<2 x double> %v) nounwind readnone ssp {
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