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AMDGPU: Fix commuting v_sub_u16
The correct commutable opcode was set to itself, so this was simply swapping the operands to commute instead of also changing the opcode to v_subrev_u16. llvm-svn: 289093
This commit is contained in:
Matt Arsenault
parent
71ed6f04a8
commit
c57e18e32f
@ -349,7 +349,7 @@ defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>;
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def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16>;
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defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>;
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defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>;
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defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16>;
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defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">;
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defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>;
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defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum>;
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defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum>;
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169
test/CodeGen/AMDGPU/sub.i16.ll
Normal file
169
test/CodeGen/AMDGPU/sub.i16.ll
Normal file
@ -0,0 +1,169 @@
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define void @v_test_sub_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
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%a = load volatile i16, i16 addrspace(1)* %gep.in0
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%b = load volatile i16, i16 addrspace(1)* %gep.in1
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%add = sub i16 %a, %b
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store i16 %add, i16 addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16_constant:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 0xffffff85, [[A]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define void @v_test_sub_i16_constant(i16 addrspace(1)* %out, i16 addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%a = load volatile i16, i16 addrspace(1)* %gep.in0
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%add = sub i16 %a, 123
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store i16 %add, i16 addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16_neg_constant:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 0x34d, [[A]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define void @v_test_sub_i16_neg_constant(i16 addrspace(1)* %out, i16 addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%a = load volatile i16, i16 addrspace(1)* %gep.in0
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%add = sub i16 %a, -845
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store i16 %add, i16 addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16_inline_63:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 0xffffffc1, [[A]]
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; VI-NEXT: buffer_store_short [[ADD]]
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define void @v_test_sub_i16_inline_63(i16 addrspace(1)* %out, i16 addrspace(1)* %in0) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%a = load volatile i16, i16 addrspace(1)* %gep.in0
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%add = sub i16 %a, 63
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store i16 %add, i16 addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16_zext_to_i32:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: buffer_store_dword [[ADD]]
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define void @v_test_sub_i16_zext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
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%a = load volatile i16, i16 addrspace(1)* %gep.in0
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%b = load volatile i16, i16 addrspace(1)* %gep.in1
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%add = sub i16 %a, %b
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%ext = zext i16 %add to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16_zext_to_i64:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI-DAG: v_sub_u16_e32 v[[ADD:[0-9]+]], [[A]], [[B]]
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; VI-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0
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; VI: buffer_store_dwordx2 v{{\[}}[[ADD]]:[[VZERO]]{{\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
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define void @v_test_sub_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
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%a = load volatile i16, i16 addrspace(1)* %gep.in0
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%b = load volatile i16, i16 addrspace(1)* %gep.in1
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%add = sub i16 %a, %b
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%ext = zext i16 %add to i64
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store i64 %ext, i64 addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16_sext_to_i32:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: v_bfe_i32 [[SEXT:v[0-9]+]], [[ADD]], 0, 16
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; VI-NEXT: buffer_store_dword [[SEXT]]
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define void @v_test_sub_i16_sext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
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%a = load i16, i16 addrspace(1)* %gep.in0
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%b = load i16, i16 addrspace(1)* %gep.in1
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%add = sub i16 %a, %b
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%ext = sext i16 %add to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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; GCN-LABEL: {{^}}v_test_sub_i16_sext_to_i64:
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; VI: flat_load_ushort [[A:v[0-9]+]]
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; VI: flat_load_ushort [[B:v[0-9]+]]
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; VI: v_sub_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
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; VI-NEXT: v_bfe_i32 v[[LO:[0-9]+]], [[ADD]], 0, 16
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; VI-NEXT: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
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; VI-NEXT: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
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define void @v_test_sub_i16_sext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i64, i64 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%gep.in1 = getelementptr inbounds i16, i16 addrspace(1)* %in1, i32 %tid
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%a = load i16, i16 addrspace(1)* %gep.in0
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%b = load i16, i16 addrspace(1)* %gep.in1
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%add = sub i16 %a, %b
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%ext = sext i16 %add to i64
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store i64 %ext, i64 addrspace(1)* %out
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ret void
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}
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@lds = addrspace(3) global [512 x i32] undef, align 4
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; GCN-LABEL: {{^}}v_test_sub_i16_constant_commute:
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; VI: v_subrev_u16_e32 v{{[0-9]+}}, 0x800, v{{[0-9]+}}
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; CI: v_subrev_i32_e32 v{{[0-9]+}}, vcc, 0x800, v{{[0-9]+}}
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define void @v_test_sub_i16_constant_commute(i16 addrspace(1)* %out, i16 addrspace(1)* %in0) #1 {
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%size = call i32 @llvm.amdgcn.groupstaticsize()
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%size.trunc = trunc i32 %size to i16
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call void asm sideeffect "; $0", "v"([512 x i32] addrspace(3)* @lds)
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
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%gep.in0 = getelementptr inbounds i16, i16 addrspace(1)* %in0, i32 %tid
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%a = load volatile i16, i16 addrspace(1)* %gep.in0
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%add = sub i16 %a, %size.trunc
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store i16 %add, i16 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.groupstaticsize() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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