RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
Code Issues Projects Releases Wiki Activity

[ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers

Browse Source 
These instructions require that the two S registers are adjacent (but not the R
registers), because only the first register is included in the encoding, but we
were not checking this in the assembler.

Differential revision: https://reviews.llvm.org/D44084

llvm-svn: 326696
This commit is contained in:
Oliver Stannard 2018-03-05 13:27:26 +00:00
parent b8ac3c4437
commit c5843bab91
2 changed files with 24 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -6631,6 +6631,24 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
"code specified");
break;
}
case ARM::VMOVRRS: {
// Source registers must be sequential.
const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
if (Sm1 != Sm + 1)
return Error(Operands[5]->getStartLoc(),
"source operands must be sequential");
break;
}
case ARM::VMOVSRR: {
// Destination registers must be sequential.
const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
if (Sm1 != Sm + 1)
return Error(Operands[3]->getStartLoc(),
"destination operands must be sequential");
break;
}
}
return false;

6
test/MC/ARM/vmov-pair-diags.s Normal file
View File

@ -0,0 +1,6 @@
@ RUN: not llvm-mc -triple armv7-eabi < %s 2>&1 | FileCheck %s
vmov r0, r1, s0, s2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operands must be sequential
vmov s0, s2, r0, r1
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: destination operands must be sequential