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[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB

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Summary:
LDRAA and LDRAB in their writeback variant should softfail when the same
register is used as result and base.

This patch adds a custom decoder that catches such case and emits a
warning when it occurs.

Differential Revision: https://reviews.llvm.org/D82541
This commit is contained in:
Victor Campos 2020-06-24 14:25:29 +01:00
parent 281e020b4e
commit c5975f74e8
3 changed files with 48 additions and 1 deletions
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2
lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -1647,6 +1647,8 @@ class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm,
let Inst{10} = 1;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
let DecoderMethod = "DecodeAuthLoadInstruction";
}
multiclass AuthLoad<bit M, string asm, Operand opr> {

36
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@ -146,6 +146,9 @@ static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
uint64_t Address,
const void *Decoder);
@ -1501,6 +1504,39 @@ static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
return Success;
}
static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr,
const void *Decoder) {
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
fieldFromInstruction(insn, 12, 9);
unsigned writeback = fieldFromInstruction(insn, 11, 1);
switch (Inst.getOpcode()) {
default:
return Fail;
case AArch64::LDRAAwriteback:
case AArch64::LDRABwriteback:
DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
Decoder);
break;
case AArch64::LDRAAindexed:
case AArch64::LDRABindexed:
break;
}
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeSImm<10>(Inst, offset, Addr, Decoder);
if (writeback && Rt == Rn && Rn != 31) {
return SoftFail;
}
return Success;
}
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr,
const void *Decoder) {

11
test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt
View File

@ -1,4 +1,13 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s 2>&1 | FileCheck %s
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0x00,0x0c,0x20,0xf8]
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0x00,0x0c,0xa0,0xf8]
# CHECK: ldraa x0, [x0, #0]!
# CHECK: ldrab x0, [x0, #0]!
[0x00,0x0c,0x20,0xf8]
[0x00,0x0c,0xa0,0xf8]
# CHECK: paciasp
# CHECK: autiasp