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new testcase.
llvm-svn: 35591
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test/CodeGen/ARM/lsr-scale-addr-mode.ll
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19
test/CodeGen/ARM/lsr-scale-addr-mode.ll
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; RUN: llvm-as < %s | llc -march=arm | grep -F 'str r2, [r0, +r3, lsl #2]'
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; Should use scaled addressing mode.
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define void @sintzero(i32* %a) {
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entry:
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store i32 0, i32* %a
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br label %cond_next
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cond_next: ; preds = %cond_next, %entry
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%indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ] ; <i32> [#uses=1]
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%tmp25 = add i32 %indvar, 1 ; <i32> [#uses=3]
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%tmp36 = getelementptr i32* %a, i32 %tmp25 ; <i32*> [#uses=1]
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store i32 0, i32* %tmp36
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icmp eq i32 %tmp25, -1 ; <i1>:0 [#uses=1]
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br i1 %0, label %return, label %cond_next
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return: ; preds = %cond_next
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ret void
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}
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