From c5fe150312ffe455f513fd3357780f1771a93e89 Mon Sep 17 00:00:00 2001 From: Stefan Pintilie Date: Wed, 13 Feb 2019 23:37:23 +0000 Subject: [PATCH] [PowerPC][NFC] Added tests for prologue and epilogue code gen. Added four test files to check the existing behaviour of prologue and epilogue code generation. This patch was done as a setup for the upcoming patch listed on Phabricator that will change how the prologue and epilogue work. The upcoming patch is: https://reviews.llvm.org/D42590 llvm-svn: 353994 --- test/CodeGen/PowerPC/CSR-fit.ll | 280 ++++++++++++++++++ test/CodeGen/PowerPC/larger-than-red-zone.ll | 88 ++++++ .../CodeGen/PowerPC/not-fixed-frame-object.ll | 91 ++++++ test/CodeGen/PowerPC/reg-scavenging.ll | 35 +++ 4 files changed, 494 insertions(+) create mode 100644 test/CodeGen/PowerPC/CSR-fit.ll create mode 100644 test/CodeGen/PowerPC/larger-than-red-zone.ll create mode 100644 test/CodeGen/PowerPC/not-fixed-frame-object.ll create mode 100644 test/CodeGen/PowerPC/reg-scavenging.ll diff --git a/test/CodeGen/PowerPC/CSR-fit.ll b/test/CodeGen/PowerPC/CSR-fit.ll new file mode 100644 index 00000000000..c6054073843 --- /dev/null +++ b/test/CodeGen/PowerPC/CSR-fit.ll @@ -0,0 +1,280 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=CHECK-PWR8 %s +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=CHECK-PWR9 %s + + +declare signext i32 @callee(i32 signext) local_unnamed_addr + +define dso_local signext i32 @caller1(i32 signext %a, i32 signext %b) local_unnamed_addr { +; CHECK-PWR8-LABEL: caller1: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr r0 +; CHECK-PWR8-NEXT: std r0, 16(r1) +; CHECK-PWR8-NEXT: stdu r1, -176(r1) +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset r14, -144 +; CHECK-PWR8-NEXT: .cfi_offset r15, -136 +; CHECK-PWR8-NEXT: std r14, 32(r1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: std r15, 40(r1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: #APP +; CHECK-PWR8-NEXT: add r3, r3, r4 +; CHECK-PWR8-NEXT: #NO_APP +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: bl callee +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: ld r15, 40(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: ld r14, 32(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: addi r1, r1, 176 +; CHECK-PWR8-NEXT: ld r0, 16(r1) +; CHECK-PWR8-NEXT: mtlr r0 +; CHECK-PWR8-NEXT: blr +; +; CHECK-PWR9-LABEL: caller1: +; CHECK-PWR9: # %bb.0: # %entry +; CHECK-PWR9-NEXT: mflr r0 +; CHECK-PWR9-NEXT: std r0, 16(r1) +; CHECK-PWR9-NEXT: stdu r1, -176(r1) +; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 +; CHECK-PWR9-NEXT: .cfi_offset lr, 16 +; CHECK-PWR9-NEXT: .cfi_offset r14, -144 +; CHECK-PWR9-NEXT: .cfi_offset r15, -136 +; CHECK-PWR9-NEXT: std r14, 32(r1) # 8-byte Folded Spill +; CHECK-PWR9-NEXT: std r15, 40(r1) # 8-byte Folded Spill +; CHECK-PWR9-NEXT: #APP +; CHECK-PWR9-NEXT: add r3, r3, r4 +; CHECK-PWR9-NEXT: #NO_APP +; CHECK-PWR9-NEXT: extsw r3, r3 +; CHECK-PWR9-NEXT: bl callee +; CHECK-PWR9-NEXT: nop +; CHECK-PWR9-NEXT: ld r15, 40(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: ld r14, 32(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: addi r1, r1, 176 +; CHECK-PWR9-NEXT: ld r0, 16(r1) +; CHECK-PWR9-NEXT: mtlr r0 +; CHECK-PWR9-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0) + ret i32 %call +} + +define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr { +; CHECK-PWR8-LABEL: caller2: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr r0 +; CHECK-PWR8-NEXT: std r0, 16(r1) +; CHECK-PWR8-NEXT: stdu r1, -176(r1) +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset f14, -144 +; CHECK-PWR8-NEXT: .cfi_offset f15, -136 +; CHECK-PWR8-NEXT: stfd f14, 32(r1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: stfd f15, 40(r1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: #APP +; CHECK-PWR8-NEXT: add r3, r3, r4 +; CHECK-PWR8-NEXT: #NO_APP +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: bl callee +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: lfd f15, 40(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: lfd f14, 32(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: addi r1, r1, 176 +; CHECK-PWR8-NEXT: ld r0, 16(r1) +; CHECK-PWR8-NEXT: mtlr r0 +; CHECK-PWR8-NEXT: blr +; +; CHECK-PWR9-LABEL: caller2: +; CHECK-PWR9: # %bb.0: # %entry +; CHECK-PWR9-NEXT: mflr r0 +; CHECK-PWR9-NEXT: std r0, 16(r1) +; CHECK-PWR9-NEXT: stdu r1, -176(r1) +; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 +; CHECK-PWR9-NEXT: .cfi_offset lr, 16 +; CHECK-PWR9-NEXT: .cfi_offset f14, -144 +; CHECK-PWR9-NEXT: .cfi_offset f15, -136 +; CHECK-PWR9-NEXT: stfd f14, 32(r1) # 8-byte Folded Spill +; CHECK-PWR9-NEXT: stfd f15, 40(r1) # 8-byte Folded Spill +; CHECK-PWR9-NEXT: #APP +; CHECK-PWR9-NEXT: add r3, r3, r4 +; CHECK-PWR9-NEXT: #NO_APP +; CHECK-PWR9-NEXT: extsw r3, r3 +; CHECK-PWR9-NEXT: bl callee +; CHECK-PWR9-NEXT: nop +; CHECK-PWR9-NEXT: lfd f15, 40(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: lfd f14, 32(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: addi r1, r1, 176 +; CHECK-PWR9-NEXT: ld r0, 16(r1) +; CHECK-PWR9-NEXT: mtlr r0 +; CHECK-PWR9-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0) + ret i32 %call +} + +define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr { +; CHECK-PWR8-LABEL: caller3: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr r0 +; CHECK-PWR8-NEXT: std r0, 16(r1) +; CHECK-PWR8-NEXT: stdu r1, -240(r1) +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset v20, -192 +; CHECK-PWR8-NEXT: .cfi_offset v21, -176 +; CHECK-PWR8-NEXT: li r5, 48 +; CHECK-PWR8-NEXT: stxvd2x v20, r1, r5 # 16-byte Folded Spill +; CHECK-PWR8-NEXT: li r5, 64 +; CHECK-PWR8-NEXT: stxvd2x v21, r1, r5 # 16-byte Folded Spill +; CHECK-PWR8-NEXT: #APP +; CHECK-PWR8-NEXT: add r3, r3, r4 +; CHECK-PWR8-NEXT: #NO_APP +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: bl callee +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: li r4, 64 +; CHECK-PWR8-NEXT: lxvd2x v21, r1, r4 # 16-byte Folded Reload +; CHECK-PWR8-NEXT: li r4, 48 +; CHECK-PWR8-NEXT: lxvd2x v20, r1, r4 # 16-byte Folded Reload +; CHECK-PWR8-NEXT: addi r1, r1, 240 +; CHECK-PWR8-NEXT: ld r0, 16(r1) +; CHECK-PWR8-NEXT: mtlr r0 +; CHECK-PWR8-NEXT: blr +; +; CHECK-PWR9-LABEL: caller3: +; CHECK-PWR9: # %bb.0: # %entry +; CHECK-PWR9-NEXT: mflr r0 +; CHECK-PWR9-NEXT: std r0, 16(r1) +; CHECK-PWR9-NEXT: stdu r1, -224(r1) +; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224 +; CHECK-PWR9-NEXT: .cfi_offset lr, 16 +; CHECK-PWR9-NEXT: .cfi_offset v20, -192 +; CHECK-PWR9-NEXT: .cfi_offset v21, -176 +; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill +; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill +; CHECK-PWR9-NEXT: #APP +; CHECK-PWR9-NEXT: add r3, r3, r4 +; CHECK-PWR9-NEXT: #NO_APP +; CHECK-PWR9-NEXT: extsw r3, r3 +; CHECK-PWR9-NEXT: bl callee +; CHECK-PWR9-NEXT: nop +; CHECK-PWR9-NEXT: lxv v21, 48(r1) # 16-byte Folded Reload +; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload +; CHECK-PWR9-NEXT: addi r1, r1, 224 +; CHECK-PWR9-NEXT: ld r0, 16(r1) +; CHECK-PWR9-NEXT: mtlr r0 +; CHECK-PWR9-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20},~{v21}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0) + ret i32 %call +} + +define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unnamed_addr { +; CHECK-PWR8-LABEL: caller4: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr r0 +; CHECK-PWR8-NEXT: std r0, 16(r1) +; CHECK-PWR8-NEXT: stdu r1, -32(r1) +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 32 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: #APP +; CHECK-PWR8-NEXT: add r3, r3, r4 +; CHECK-PWR8-NEXT: #NO_APP +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: bl callee +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: addi r1, r1, 32 +; CHECK-PWR8-NEXT: ld r0, 16(r1) +; CHECK-PWR8-NEXT: mtlr r0 +; CHECK-PWR8-NEXT: blr +; +; CHECK-PWR9-LABEL: caller4: +; CHECK-PWR9: # %bb.0: # %entry +; CHECK-PWR9-NEXT: mflr r0 +; CHECK-PWR9-NEXT: std r0, 16(r1) +; CHECK-PWR9-NEXT: stdu r1, -32(r1) +; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 32 +; CHECK-PWR9-NEXT: .cfi_offset lr, 16 +; CHECK-PWR9-NEXT: #APP +; CHECK-PWR9-NEXT: add r3, r3, r4 +; CHECK-PWR9-NEXT: #NO_APP +; CHECK-PWR9-NEXT: extsw r3, r3 +; CHECK-PWR9-NEXT: bl callee +; CHECK-PWR9-NEXT: nop +; CHECK-PWR9-NEXT: addi r1, r1, 32 +; CHECK-PWR9-NEXT: ld r0, 16(r1) +; CHECK-PWR9-NEXT: mtlr r0 +; CHECK-PWR9-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{vs52},~{vs53}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0) + ret i32 %call +} + +define dso_local signext i32 @caller_mixed(i32 signext %a, i32 signext %b) local_unnamed_addr { +; CHECK-PWR8-LABEL: caller_mixed: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr r0 +; CHECK-PWR8-NEXT: std r0, 16(r1) +; CHECK-PWR8-NEXT: stdu r1, -528(r1) +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 528 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset r14, -288 +; CHECK-PWR8-NEXT: .cfi_offset f14, -144 +; CHECK-PWR8-NEXT: .cfi_offset v20, -480 +; CHECK-PWR8-NEXT: li r5, 48 +; CHECK-PWR8-NEXT: std r14, 240(r1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: stfd f14, 384(r1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: stxvd2x v20, r1, r5 # 16-byte Folded Spill +; CHECK-PWR8-NEXT: #APP +; CHECK-PWR8-NEXT: add r3, r3, r4 +; CHECK-PWR8-NEXT: #NO_APP +; CHECK-PWR8-NEXT: extsw r3, r3 +; CHECK-PWR8-NEXT: bl callee +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: li r4, 48 +; CHECK-PWR8-NEXT: lfd f14, 384(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: ld r14, 240(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: lxvd2x v20, r1, r4 # 16-byte Folded Reload +; CHECK-PWR8-NEXT: addi r1, r1, 528 +; CHECK-PWR8-NEXT: ld r0, 16(r1) +; CHECK-PWR8-NEXT: mtlr r0 +; CHECK-PWR8-NEXT: blr +; +; CHECK-PWR9-LABEL: caller_mixed: +; CHECK-PWR9: # %bb.0: # %entry +; CHECK-PWR9-NEXT: mflr r0 +; CHECK-PWR9-NEXT: std r0, 16(r1) +; CHECK-PWR9-NEXT: stdu r1, -512(r1) +; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 512 +; CHECK-PWR9-NEXT: .cfi_offset lr, 16 +; CHECK-PWR9-NEXT: .cfi_offset r14, -288 +; CHECK-PWR9-NEXT: .cfi_offset f14, -144 +; CHECK-PWR9-NEXT: .cfi_offset v20, -480 +; CHECK-PWR9-NEXT: std r14, 224(r1) # 8-byte Folded Spill +; CHECK-PWR9-NEXT: stfd f14, 368(r1) # 8-byte Folded Spill +; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill +; CHECK-PWR9-NEXT: #APP +; CHECK-PWR9-NEXT: add r3, r3, r4 +; CHECK-PWR9-NEXT: #NO_APP +; CHECK-PWR9-NEXT: extsw r3, r3 +; CHECK-PWR9-NEXT: bl callee +; CHECK-PWR9-NEXT: nop +; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload +; CHECK-PWR9-NEXT: lfd f14, 368(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: ld r14, 224(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: addi r1, r1, 512 +; CHECK-PWR9-NEXT: ld r0, 16(r1) +; CHECK-PWR9-NEXT: mtlr r0 +; CHECK-PWR9-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{f14},~{v20},~{vs53}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0) + ret i32 %call +} + + diff --git a/test/CodeGen/PowerPC/larger-than-red-zone.ll b/test/CodeGen/PowerPC/larger-than-red-zone.ll new file mode 100644 index 00000000000..2649671ea9a --- /dev/null +++ b/test/CodeGen/PowerPC/larger-than-red-zone.ll @@ -0,0 +1,88 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s + +define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr { +; CHECK-LABEL: caller: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -320(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 320 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: .cfi_offset r14, -288 +; CHECK-NEXT: .cfi_offset r15, -280 +; CHECK-NEXT: .cfi_offset r16, -272 +; CHECK-NEXT: .cfi_offset r17, -264 +; CHECK-NEXT: .cfi_offset r18, -256 +; CHECK-NEXT: .cfi_offset r19, -248 +; CHECK-NEXT: .cfi_offset r20, -240 +; CHECK-NEXT: .cfi_offset r21, -232 +; CHECK-NEXT: .cfi_offset r22, -224 +; CHECK-NEXT: .cfi_offset r23, -216 +; CHECK-NEXT: .cfi_offset r24, -208 +; CHECK-NEXT: .cfi_offset r25, -200 +; CHECK-NEXT: .cfi_offset r26, -192 +; CHECK-NEXT: .cfi_offset r27, -184 +; CHECK-NEXT: .cfi_offset r28, -176 +; CHECK-NEXT: .cfi_offset r29, -168 +; CHECK-NEXT: .cfi_offset r30, -160 +; CHECK-NEXT: .cfi_offset r31, -152 +; CHECK-NEXT: .cfi_offset f14, -144 +; CHECK-NEXT: std r14, 32(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r15, 40(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r16, 48(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r17, 56(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r18, 64(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r19, 72(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r20, 80(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r21, 88(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r22, 96(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r23, 104(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r24, 112(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r25, 120(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r26, 128(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r27, 136(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r28, 144(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r29, 152(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r31, 168(r1) # 8-byte Folded Spill +; CHECK-NEXT: stfd f14, 176(r1) # 8-byte Folded Spill +; CHECK-NEXT: #APP +; CHECK-NEXT: add r3, r3, r4 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: bl callee +; CHECK-NEXT: nop +; CHECK-NEXT: lfd f14, 176(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r31, 168(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r30, 160(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r29, 152(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r28, 144(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r27, 136(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r26, 128(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r25, 120(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r24, 112(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r23, 104(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r22, 96(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r21, 88(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r20, 80(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r19, 72(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r18, 64(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r17, 56(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r16, 48(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r15, 40(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r14, 32(r1) # 8-byte Folded Reload +; CHECK-NEXT: addi r1, r1, 320 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{f14}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0) + ret i32 %call +} + +declare signext i32 @callee(i32 signext) local_unnamed_addr + + diff --git a/test/CodeGen/PowerPC/not-fixed-frame-object.ll b/test/CodeGen/PowerPC/not-fixed-frame-object.ll new file mode 100644 index 00000000000..7dce9e5a8aa --- /dev/null +++ b/test/CodeGen/PowerPC/not-fixed-frame-object.ll @@ -0,0 +1,91 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s + +define dso_local signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr { +; CHECK-LABEL: caller: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -192(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 192 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: .cfi_offset r14, -144 +; CHECK-NEXT: .cfi_offset r15, -136 +; CHECK-NEXT: .cfi_offset r16, -128 +; CHECK-NEXT: .cfi_offset r17, -120 +; CHECK-NEXT: .cfi_offset r18, -112 +; CHECK-NEXT: .cfi_offset r19, -104 +; CHECK-NEXT: .cfi_offset r20, -96 +; CHECK-NEXT: .cfi_offset r21, -88 +; CHECK-NEXT: .cfi_offset r22, -80 +; CHECK-NEXT: .cfi_offset r23, -72 +; CHECK-NEXT: .cfi_offset r24, -64 +; CHECK-NEXT: .cfi_offset r25, -56 +; CHECK-NEXT: .cfi_offset r26, -48 +; CHECK-NEXT: .cfi_offset r27, -40 +; CHECK-NEXT: .cfi_offset r28, -32 +; CHECK-NEXT: .cfi_offset r29, -24 +; CHECK-NEXT: .cfi_offset r30, -16 +; CHECK-NEXT: .cfi_offset r31, -8 +; CHECK-NEXT: std r5, 32(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r3, 40(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r14, 48(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r15, 56(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r16, 64(r1) # 8-byte Folded Spill +; CHECK-NEXT: mr r0, r4 +; CHECK-NEXT: ld r3, 40(r1) # 8-byte Folded Reload +; CHECK-NEXT: std r17, 72(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r18, 80(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r19, 88(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r20, 96(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r21, 104(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r22, 112(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r23, 120(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r24, 128(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r25, 136(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r26, 144(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r27, 152(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r28, 160(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r29, 168(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r30, 176(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r31, 184(r1) # 8-byte Folded Spill +; CHECK-NEXT: #APP +; CHECK-NEXT: add r3, r3, r0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: ld r4, 40(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: mr r5, r0 +; CHECK-NEXT: bl callee +; CHECK-NEXT: nop +; CHECK-NEXT: ld r31, 184(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r30, 176(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r29, 168(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r28, 160(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r27, 152(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r26, 144(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r25, 136(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r24, 128(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r23, 120(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r22, 112(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r21, 104(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r20, 96(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r19, 88(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r18, 80(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r17, 72(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r16, 64(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r15, 56(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r14, 48(r1) # 8-byte Folded Reload +; CHECK-NEXT: addi r1, r1, 192 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0, i32 signext %a, i32 signext %b, i32 signext %c) + ret i32 %call +} + +declare signext i32 @callee(i32 signext, i32 signext, i32 signext, i32 signext) local_unnamed_addr + diff --git a/test/CodeGen/PowerPC/reg-scavenging.ll b/test/CodeGen/PowerPC/reg-scavenging.ll new file mode 100644 index 00000000000..6a32c176dc4 --- /dev/null +++ b/test/CodeGen/PowerPC/reg-scavenging.ll @@ -0,0 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s + +define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr { +; CHECK-LABEL: caller: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -240(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 240 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: .cfi_offset v20, -192 +; CHECK-NEXT: li r5, 48 +; CHECK-NEXT: stxvd2x v20, r1, r5 # 16-byte Folded Spill +; CHECK-NEXT: #APP +; CHECK-NEXT: add r3, r3, r4 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: bl callee +; CHECK-NEXT: nop +; CHECK-NEXT: li r4, 48 +; CHECK-NEXT: lxvd2x v20, r1, r4 # 16-byte Folded Reload +; CHECK-NEXT: addi r1, r1, 240 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20}"(i32 %a, i32 %b) + %call = tail call signext i32 @callee(i32 signext %0) + ret i32 %call +} + +declare signext i32 @callee(i32 signext) local_unnamed_addr +