Fix one more batch of X86 tests to be register allocation dependent.

llvm-svn: 128919

test/CodeGen/X86/2008-02-22-ReMatBug.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -stats |& grep {Number of re-materialization} | grep 2
+; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of re-materialization} | grep 2
 ; rdar://5761454
 
 	%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }

test/CodeGen/X86/2008-03-18-CoalescerBug.ll

@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep movss | count 1
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -stats |& grep {Number of re-materialization} | grep 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -regalloc=linearscan | grep movss | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -regalloc=linearscan -stats |& grep {Number of re-materialization} | grep 1
 
 	%struct..0objc_object = type opaque
 	%struct.OhBoy = type {  }

test/CodeGen/X86/2008-09-18-inline-asm-2.ll

@@ -1,5 +1,7 @@
-; RUN: llc < %s -march=x86 | grep "#%ebp %edi %ebx 8(%esi) %eax %dl"
-; RUN: llc < %s -march=x86 -regalloc=fast  | grep "#%ebx %esi %edi 8(%ebp) %eax %dl"
+; RUN: llc < %s -march=x86 -regalloc=linearscan | grep "#%ebp %edi %ebx 8(%esi) %eax %dl"
+; RUN: llc < %s -march=x86 -regalloc=fast       | grep "#%ebx %esi %edi 8(%ebp) %eax %dl"
+; RUN: llc < %s -march=x86 -regalloc=basic      | grep "#%ebp %esi %edx 8(%edi) %eax %bl"
+; RUN: llc < %s -march=x86 -regalloc=greedy     | grep "#%edx %edi %ebp 8(%esi) %eax %bl"
 
 ; The 1st, 2nd, 3rd and 5th registers above must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th

test/CodeGen/X86/2009-03-16-SpillerBug.ll

@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -stats |& grep virtregrewriter | not grep {stores unfolded}
+; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=linearscan -stats |& grep virtregrewriter | not grep {stores unfolded}
 ; rdar://6682365
 
 ; Do not clobber a register if another spill slot is available in it and it's marked "do not clobber".

test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll

@@ -11,7 +11,7 @@
 ; Move return address (76(%esp)) to a temporary register (%ebp)
 ; CHECK: movl 76(%esp), [[REGISTER:%[a-z]+]]
 ; Overwrite return addresss
-; CHECK: movl %ebx, 76(%esp)
+; CHECK: movl [[EBX:%[a-z]+]], 76(%esp)
 ; Move return address from temporary register (%ebp) to new stack location (60(%esp))
 ; CHECK: movl [[REGISTER]], 60(%esp)
 

test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll

@@ -31,18 +31,19 @@ entry:
         ret void
 }
 
+; CHECK: ti64
 define void @ti64(double %a, double %b) nounwind {
 entry:
         %tmp1 = bitcast double %a to <1 x i64>
         %tmp2 = bitcast double %b to <1 x i64>
         %tmp3 = add <1 x i64> %tmp1, %tmp2
-; CHECK:  addq  %rax, %rcx
+; CHECK:  addq
         store <1 x i64> %tmp3, <1 x i64>* null
         ret void
 }
 
 ; MMX intrinsics calls get us MMX instructions.
-
+; CHECK: ti8a
 define void @ti8a(double %a, double %b) nounwind {
 entry:
         %tmp1 = bitcast double %a to x86_mmx

test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll

@@ -22,8 +22,8 @@ while.end:                                        ; preds = %while.cond, %entry
   %conv = zext i32 %v to i64                      ; <i64> [#uses=1]
   %conv14 = zext i32 %div11 to i64                ; <i64> [#uses=1]
 ; Verify that we don't clobber %eax after putting the imulq result in %rax
-; CHECK: imulq	%r{{.}}x, %r[[RES:.]]x
-; CHECK-NOT: movl	{{.*}}, %e[[RES]]x
+; CHECK: imulq	%r{{.}}x, %r[[RES:..]]
+; CHECK-NOT: movl	{{.*}}, %e[[RES]]
 ; CHECK: div
   %mul = mul i64 %conv14, %conv                   ; <i64> [#uses=1]
   %conv16 = zext i32 %div to i64                  ; <i64> [#uses=1]

test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll

@@ -19,8 +19,8 @@ entry:
 }
 
 ; CHECK: movq	___stack_chk_guard@GOTPCREL(%rip), %rax
-; CHECK: movb   38(%rsp), %bl
-; CHECK: movb   8(%rsp), %dl
-; CHECK: movb   %dl, 8(%rsp)
-; CHECK: movb   %bl, 38(%rsp)
+; CHECK: movb   38(%rsp), [[R0:%.+]]
+; CHECK: movb   8(%rsp), [[R1:%.+]]
+; CHECK: movb   [[R1]], 8(%rsp)
+; CHECK: movb   [[R0]], 38(%rsp)
 ; CHECK: callq	___stack_chk_fail