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[RISC-V] Fixed alias for addi x2, x2, 0

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A missing check for non-zero immediate in MCOperandPredicate
caused c.addi16sp sp, 0 to be selected which is not a valid
instruction.

llvm-svn: 339381
This commit is contained in:
Ana Pazos 2018-08-09 20:51:53 +00:00
parent ba797dbf52
commit c63c7fe0e5
2 changed files with 4 additions and 1 deletions
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2
lib/Target/RISCV/RISCVInstrInfoC.td
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@ -187,7 +187,7 @@ def simm10_lsb0000nonzero : Operand<XLenVT>,
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return isShiftedInt<6, 4>(Imm);
return isShiftedInt<6, 4>(Imm) && (Imm != 0);
}];
}

3
test/MC/RISCV/rv32c-aliases-valid.s
View File

@ -60,3 +60,6 @@ li x12, -0x80000000
li x12, 0x80000000
# CHECK-EXPAND: c.li a2, -1
li x12, 0xFFFFFFFF
# CHECK-EXPAND: c.mv sp, sp
addi x2, x2, 0