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Fix 80-column violation and extraneous brackets.
llvm-svn: 146566
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1de7ae0e43
commit
c642144c4e
@ -178,8 +178,9 @@ class ARMFastISel : public FastISel {
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool isZExt);
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bool isZExt);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment = 0,
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
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bool isZExt = true, bool allocReg = true);
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unsigned Alignment = 0, bool isZExt = true,
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bool allocReg = true);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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unsigned Alignment = 0);
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@ -1027,11 +1028,11 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
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}
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}
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break;
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break;
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case MVT::f64:
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case MVT::f64:
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if (Alignment && Alignment < 4) {
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// FIXME: Unaligned loads need special handling. Doublewords require
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// FIXME: Unaligned loads need special handling. Doublewords require
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// word-alignment.
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// word-alignment.
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if (Alignment && Alignment < 4)
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return false;
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return false;
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}
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Opc = ARM::VLDRD;
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Opc = ARM::VLDRD;
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RC = TLI.getRegClassFor(VT);
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RC = TLI.getRegClassFor(VT);
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break;
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break;
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@ -1145,9 +1146,9 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
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if (!Subtarget->hasVFP2()) return false;
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if (!Subtarget->hasVFP2()) return false;
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// FIXME: Unaligned stores need special handling. Doublewords require
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// FIXME: Unaligned stores need special handling. Doublewords require
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// word-alignment.
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// word-alignment.
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if (Alignment && Alignment < 4) {
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if (Alignment && Alignment < 4)
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return false;
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return false;
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}
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StrOpc = ARM::VSTRD;
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StrOpc = ARM::VSTRD;
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break;
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break;
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}
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}
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