RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 12:43:36 +01:00
Code Issues Projects Releases Wiki Activity

[InstCombine] regenerate test checks; NFC

Browse Source
This commit is contained in:
Sanjay Patel 2020-09-19 10:43:18 -04:00
parent 883809adba
commit c6580be685
1 changed files with 25 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
test/Transforms/InstCombine/zext-or-icmp.ll
View File

@ -1,28 +1,45 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
; Remove an icmp by using its operand in the subsequent logic directly.
define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) {
; CHECK-LABEL: @zext_or_icmp_icmp(
; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1
; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0
; CHECK-NEXT: [[TOBOOL22:%.*]] = zext i1 [[TOBOOL2]] to i8
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[MASK]], 1
; CHECK-NEXT: [[ZEXT3:%.*]] = or i8 [[TMP1]], [[TOBOOL22]]
; CHECK-NEXT: ret i8 [[ZEXT3]]
;
%mask = and i8 %a, 1
%toBool1 = icmp eq i8 %mask, 0
%toBool2 = icmp eq i8 %b, 0
%bothCond = or i1 %toBool1, %toBool2
%zext = zext i1 %bothCond to i8
ret i8 %zext
; CHECK-LABEL: zext_or_icmp_icmp(
; CHECK-NEXT: %mask = and i8 %a, 1
; CHECK-NEXT: %toBool2 = icmp eq i8 %b, 0
; CHECK-NEXT: %toBool22 = zext i1 %toBool2 to i8
; CHECK-NEXT: %1 = xor i8 %mask, 1
; CHECK-NEXT: %zext3 = or i8 %1, %toBool22
; CHECK-NEXT: ret i8 %zext
}
; Here, widening the or from i1 to i32 and removing one of the icmps would
; widen an undef value (created by the out-of-range shift), increasing the
; range of valid values for the return, so we can't do it.
define i32 @dont_widen_undef() {
; CHECK-LABEL: @dont_widen_undef(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[BLOCK2:%.*]]
; CHECK: block1:
; CHECK-NEXT: br label [[BLOCK2]]
; CHECK: block2:
; CHECK-NEXT: [[CMP_I:%.*]] = phi i1 [ false, [[BLOCK1:%.*]] ], [ true, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[M_011:%.*]] = phi i32 [ 0, [[BLOCK1]] ], [ 33, [[ENTRY]] ]
; CHECK-NEXT: [[M_1_OP:%.*]] = lshr i32 1, [[M_011]]
; CHECK-NEXT: [[SEXT_MASK:%.*]] = and i32 [[M_1_OP]], 65535
; CHECK-NEXT: [[CMP115:%.*]] = icmp ne i32 [[SEXT_MASK]], 0
; CHECK-NEXT: [[CMP1:%.*]] = or i1 [[CMP_I]], [[CMP115]]
; CHECK-NEXT: [[CONV2:%.*]] = zext i1 [[CMP1]] to i32
; CHECK-NEXT: ret i32 [[CONV2]]
;
entry:
br label %block2
@ -38,14 +55,4 @@ block2:
%cmp1 = or i1 %cmp.i, %cmp115
%conv2 = zext i1 %cmp1 to i32
ret i32 %conv2
; CHECK-LABEL: dont_widen_undef(
; CHECK: %cmp.i = phi i1 [ false, %block1 ], [ true, %entry ]
; CHECK-NEXT: %m.011 = phi i32 [ 0, %block1 ], [ 33, %entry ]
; CHECK-NEXT: %m.1.op = lshr i32 1, %m.011
; CHECK-NEXT: %sext.mask = and i32 %m.1.op, 65535
; CHECK-NEXT: %cmp115 = icmp ne i32 %sext.mask, 0
; CHECK-NEXT: %cmp1 = or i1 %cmp.i, %cmp115
; CHECK-NEXT: %conv2 = zext i1 %cmp1 to i32
; CHECK-NEXT: ret i32 %conv2
}