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[RISCV] Fix wrong CFI directives
Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723
This commit is contained in:
Luís Marques
parent
15c476d25a
commit
c66d83c8cc
@ -233,8 +233,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
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}
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}
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// FIXME Fix emission of .cfi_restore and .cfi_def_cfa CFI directives that can
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// incorrectly affect subsequent basic blocks.
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void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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@ -242,7 +240,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineFrameInfo &MFI = MF.getFrameInfo();
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auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
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DebugLoc DL = MBBI->getDebugLoc();
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const RISCVInstrInfo *TII = STI.getInstrInfo();
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Register FPReg = getFPReg(STI);
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Register SPReg = getSPReg(STI);
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@ -271,51 +268,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
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MachineInstr::FrameDestroy);
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// Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA
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if (!hasFP(MF)) {
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unsigned CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, -FirstSPAdjustAmount));
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BuildMI(MBB, LastFrameDestroy, DL,
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TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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if (hasFP(MF)) {
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// To find the instruction restoring FP from stack.
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for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
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if (I->mayLoad() && I->getOperand(0).isReg()) {
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Register DestReg = I->getOperand(0).getReg();
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if (DestReg == FPReg) {
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// If there is frame pointer, after restoring $fp registers, we
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// need adjust CFA back to the correct sp-based offset.
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// Emit ".cfi_def_cfa $sp, CFAOffset"
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uint64_t CFAOffset =
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FirstSPAdjustAmount
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? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
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: -FPOffset;
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
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nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
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BuildMI(MBB, std::next(I), DL,
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TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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break;
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}
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}
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}
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}
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// Add CFI directives for callee-saved registers.
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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// Iterate over list of callee-saved registers and emit .cfi_restore
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// directives.
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for (const auto &Entry : CSI) {
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Register Reg = Entry.getReg();
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
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nullptr, RI->getDwarfRegNum(Reg, true)));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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if (FirstSPAdjustAmount)
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@ -323,13 +275,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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// Deallocate stack
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adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
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// After restoring $sp, we need to adjust CFA to $(sp + 0)
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// Emit ".cfi_def_cfa_offset 0"
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unsigned CFIIndex =
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MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
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@ -40,11 +40,7 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
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; RV32I-NEXT: lw s1, 4(sp)
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: .cfi_restore ra
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; RV32I-NEXT: .cfi_restore s0
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; RV32I-NEXT: .cfi_restore s1
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: .cfi_def_cfa_offset 0
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB0_4: # %lpad
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; RV32I-NEXT: .Ltmp4:
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@ -81,11 +77,7 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
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; RV64I-NEXT: ld s1, 8(sp)
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; RV64I-NEXT: ld s0, 16(sp)
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; RV64I-NEXT: ld ra, 24(sp)
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; RV64I-NEXT: .cfi_restore ra
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; RV64I-NEXT: .cfi_restore s0
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; RV64I-NEXT: .cfi_restore s1
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; RV64I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: .cfi_def_cfa_offset 0
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB0_4: # %lpad
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; RV64I-NEXT: .Ltmp4:
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@ -119,12 +111,10 @@ end2:
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define internal void @callee(i1* %p) {
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; RV32I-LABEL: callee:
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; RV32I: # %bb.0:
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; RV32I-NEXT: .cfi_def_cfa_offset 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: callee:
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; RV64I: # %bb.0:
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; RV64I-NEXT: .cfi_def_cfa_offset 0
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; RV64I-NEXT: ret
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ret void
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}
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@ -9,12 +9,10 @@
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define void @trivial() {
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; RV32-LABEL: trivial:
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; RV32: # %bb.0:
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; RV32-NEXT: .cfi_def_cfa_offset 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: trivial:
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; RV64: # %bb.0:
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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;
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; RV32-WITHFP-LABEL: trivial:
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@ -28,12 +26,8 @@ define void @trivial() {
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; RV32-WITHFP-NEXT: addi s0, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: .cfi_restore ra
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; RV32-WITHFP-NEXT: .cfi_restore s0
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV32-WITHFP-NEXT: ret
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;
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; RV64-WITHFP-LABEL: trivial:
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@ -47,12 +41,8 @@ define void @trivial() {
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; RV64-WITHFP-NEXT: addi s0, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: .cfi_restore ra
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; RV64-WITHFP-NEXT: .cfi_restore s0
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV64-WITHFP-NEXT: ret
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ret void
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}
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@ -75,12 +65,8 @@ define void @stack_alloc(i32 signext %size) {
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; RV32-NEXT: call callee_with_args
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; RV32-NEXT: addi sp, s0, -16
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; RV32-NEXT: lw s0, 8(sp)
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; RV32-NEXT: .cfi_def_cfa sp, 16
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: .cfi_restore ra
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; RV32-NEXT: .cfi_restore s0
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: .cfi_def_cfa_offset 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: stack_alloc:
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@ -105,12 +91,8 @@ define void @stack_alloc(i32 signext %size) {
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; RV64-NEXT: call callee_with_args
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; RV64-NEXT: addi sp, s0, -16
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; RV64-NEXT: ld s0, 0(sp)
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; RV64-NEXT: .cfi_def_cfa sp, 16
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: .cfi_restore s0
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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;
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; RV32-WITHFP-LABEL: stack_alloc:
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@ -130,12 +112,8 @@ define void @stack_alloc(i32 signext %size) {
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; RV32-WITHFP-NEXT: call callee_with_args
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; RV32-WITHFP-NEXT: addi sp, s0, -16
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: .cfi_restore ra
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; RV32-WITHFP-NEXT: .cfi_restore s0
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV32-WITHFP-NEXT: ret
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;
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; RV64-WITHFP-LABEL: stack_alloc:
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@ -160,12 +138,8 @@ define void @stack_alloc(i32 signext %size) {
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; RV64-WITHFP-NEXT: call callee_with_args
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; RV64-WITHFP-NEXT: addi sp, s0, -16
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: .cfi_restore ra
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; RV64-WITHFP-NEXT: .cfi_restore s0
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV64-WITHFP-NEXT: ret
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entry:
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%0 = alloca i8, i32 %size, align 16
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@ -173,8 +147,6 @@ entry:
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ret void
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}
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; FIXME: fix use of .cfi_restore with wrong CFAs
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define void @branch_and_tail_call(i1 %a) {
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; RV32-LABEL: branch_and_tail_call:
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; RV32: # %bb.0:
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@ -186,16 +158,12 @@ define void @branch_and_tail_call(i1 %a) {
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; RV32-NEXT: beqz a0, .LBB2_2
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; RV32-NEXT: # %bb.1: # %blue_pill
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: .cfi_restore ra
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: .cfi_def_cfa_offset 0
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; RV32-NEXT: tail callee1
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; RV32-NEXT: .LBB2_2: # %red_pill
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; RV32-NEXT: call callee2
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: .cfi_restore ra
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: .cfi_def_cfa_offset 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: branch_and_tail_call:
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@ -208,16 +176,12 @@ define void @branch_and_tail_call(i1 %a) {
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; RV64-NEXT: beqz a0, .LBB2_2
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; RV64-NEXT: # %bb.1: # %blue_pill
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: tail callee1
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; RV64-NEXT: .LBB2_2: # %red_pill
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; RV64-NEXT: call callee2
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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;
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; RV32-WITHFP-LABEL: branch_and_tail_call:
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@ -234,22 +198,14 @@ define void @branch_and_tail_call(i1 %a) {
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; RV32-WITHFP-NEXT: beqz a0, .LBB2_2
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; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: .cfi_restore ra
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; RV32-WITHFP-NEXT: .cfi_restore s0
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV32-WITHFP-NEXT: tail callee1
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; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill
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; RV32-WITHFP-NEXT: call callee2
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; RV32-WITHFP-NEXT: lw s0, 8(sp)
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; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV32-WITHFP-NEXT: lw ra, 12(sp)
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; RV32-WITHFP-NEXT: .cfi_restore ra
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; RV32-WITHFP-NEXT: .cfi_restore s0
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; RV32-WITHFP-NEXT: addi sp, sp, 16
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; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV32-WITHFP-NEXT: ret
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;
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; RV64-WITHFP-LABEL: branch_and_tail_call:
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@ -266,22 +222,14 @@ define void @branch_and_tail_call(i1 %a) {
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; RV64-WITHFP-NEXT: beqz a0, .LBB2_2
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; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: .cfi_restore ra
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; RV64-WITHFP-NEXT: .cfi_restore s0
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV64-WITHFP-NEXT: tail callee1
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; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill
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; RV64-WITHFP-NEXT: call callee2
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; RV64-WITHFP-NEXT: ld s0, 0(sp)
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; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
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; RV64-WITHFP-NEXT: ld ra, 8(sp)
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; RV64-WITHFP-NEXT: .cfi_restore ra
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; RV64-WITHFP-NEXT: .cfi_restore s0
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; RV64-WITHFP-NEXT: addi sp, sp, 16
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; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV64-WITHFP-NEXT: ret
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br i1 %a, label %blue_pill, label %red_pill
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blue_pill:
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@ -16,7 +16,6 @@ define void @test() {
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; RV32I-FPELIM-NEXT: lui a0, 74565
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; RV32I-FPELIM-NEXT: addi a0, a0, 1664
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; RV32I-FPELIM-NEXT: add sp, sp, a0
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: test:
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@ -36,12 +35,8 @@ define void @test() {
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; RV32I-WITHFP-NEXT: addi a0, a0, -352
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; RV32I-WITHFP-NEXT: add sp, sp, a0
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; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
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; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032
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; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
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; RV32I-WITHFP-NEXT: .cfi_restore ra
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; RV32I-WITHFP-NEXT: .cfi_restore s0
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; RV32I-WITHFP-NEXT: addi sp, sp, 2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV32I-WITHFP-NEXT: ret
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%tmp = alloca [ 305419896 x i8 ] , align 4
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ret void
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@ -77,13 +72,9 @@ define void @test_emergency_spill_slot(i32 %a) {
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; RV32I-FPELIM-NEXT: lui a0, 97
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; RV32I-FPELIM-NEXT: addi a0, a0, 672
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; RV32I-FPELIM-NEXT: add sp, sp, a0
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-FPELIM-NEXT: lw s1, 2024(sp)
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; RV32I-FPELIM-NEXT: lw s0, 2028(sp)
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; RV32I-FPELIM-NEXT: .cfi_restore s0
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; RV32I-FPELIM-NEXT: .cfi_restore s1
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; RV32I-FPELIM-NEXT: addi sp, sp, 2032
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
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@ -123,14 +114,8 @@ define void @test_emergency_spill_slot(i32 %a) {
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; RV32I-WITHFP-NEXT: lw s2, 2016(sp)
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; RV32I-WITHFP-NEXT: lw s1, 2020(sp)
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; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
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; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032
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; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
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; RV32I-WITHFP-NEXT: .cfi_restore ra
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; RV32I-WITHFP-NEXT: .cfi_restore s0
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; RV32I-WITHFP-NEXT: .cfi_restore s1
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; RV32I-WITHFP-NEXT: .cfi_restore s2
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||||
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
|
||||
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
|
||||
; RV32I-WITHFP-NEXT: ret
|
||||
%data = alloca [ 100000 x i32 ] , align 4
|
||||
%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
|
||||
|
||||
@ -22,7 +22,6 @@ define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
|
||||
; RV32I-NEXT: sw a3, 4(a0)
|
||||
; RV32I-NEXT: sw a3, 0(a1)
|
||||
; RV32I-NEXT: sw a2, 4(a1)
|
||||
; RV32I-NEXT: .cfi_def_cfa_offset 0
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: test1:
|
||||
@ -38,7 +37,6 @@ define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
|
||||
; RV64I-NEXT: sw a3, 4(a0)
|
||||
; RV64I-NEXT: sw a3, 0(a1)
|
||||
; RV64I-NEXT: sw a2, 4(a1)
|
||||
; RV64I-NEXT: .cfi_def_cfa_offset 0
|
||||
; RV64I-NEXT: ret
|
||||
entry:
|
||||
%s = load [65536 x i32]*, [65536 x i32]** %sp
|
||||
@ -74,7 +72,6 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
|
||||
; RV32I-NEXT: mv a3, a4
|
||||
; RV32I-NEXT: blt a3, a2, .LBB1_1
|
||||
; RV32I-NEXT: .LBB1_2: # %while_end
|
||||
; RV32I-NEXT: .cfi_def_cfa_offset 0
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: test2:
|
||||
@ -99,7 +96,6 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
|
||||
; RV64I-NEXT: sext.w a4, a3
|
||||
; RV64I-NEXT: blt a4, a2, .LBB1_1
|
||||
; RV64I-NEXT: .LBB1_2: # %while_end
|
||||
; RV64I-NEXT: .cfi_def_cfa_offset 0
|
||||
; RV64I-NEXT: ret
|
||||
entry:
|
||||
%s = load [65536 x i32]*, [65536 x i32]** %sp
|
||||
|
||||
@ -53,7 +53,6 @@ define i32 @va1(i8* %fmt, ...) {
|
||||
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24
|
||||
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
|
||||
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
|
||||
; ILP32-ILP32F-FPELIM-NEXT: .cfi_def_cfa_offset 0
|
||||
; ILP32-ILP32F-FPELIM-NEXT: ret
|
||||
;
|
||||
; ILP32-ILP32F-WITHFP-LABEL: va1:
|
||||
@ -77,12 +76,8 @@ define i32 @va1(i8* %fmt, ...) {
|
||||
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
|
||||
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
|
||||
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa sp, 16
|
||||
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore ra
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore s0
|
||||
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 0
|
||||
; ILP32-ILP32F-WITHFP-NEXT: ret
|
||||
;
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1:
|
||||
@ -100,7 +95,6 @@ define i32 @va1(i8* %fmt, ...) {
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 0
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
|
||||
;
|
||||
; LP64-LP64F-LP64D-FPELIM-LABEL: va1:
|
||||
@ -119,7 +113,6 @@ define i32 @va1(i8* %fmt, ...) {
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp)
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 0
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
|
||||
;
|
||||
; LP64-LP64F-LP64D-WITHFP-LABEL: va1:
|
||||
@ -144,12 +137,8 @@ define i32 @va1(i8* %fmt, ...) {
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa sp, 32
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore ra
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore s0
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 0
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: ret
|
||||
%va = alloca i8*, align 4
|
||||
%1 = bitcast i8** %va to i8*
|
||||
@ -1809,7 +1798,6 @@ define i32 @va_large_stack(i8* %fmt, ...) {
|
||||
; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414
|
||||
; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 304
|
||||
; ILP32-ILP32F-FPELIM-NEXT: add sp, sp, a1
|
||||
; ILP32-ILP32F-FPELIM-NEXT: .cfi_def_cfa_offset 0
|
||||
; ILP32-ILP32F-FPELIM-NEXT: ret
|
||||
;
|
||||
; ILP32-ILP32F-WITHFP-LABEL: va_large_stack:
|
||||
@ -1842,12 +1830,8 @@ define i32 @va_large_stack(i8* %fmt, ...) {
|
||||
; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, -1728
|
||||
; ILP32-ILP32F-WITHFP-NEXT: add sp, sp, a1
|
||||
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 1992(sp)
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa sp, 2000
|
||||
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 1996(sp)
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore ra
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore s0
|
||||
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 2032
|
||||
; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 0
|
||||
; ILP32-ILP32F-WITHFP-NEXT: ret
|
||||
;
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va_large_stack:
|
||||
@ -1893,7 +1877,6 @@ define i32 @va_large_stack(i8* %fmt, ...) {
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a1, 304
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add sp, sp, a1
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 0
|
||||
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
|
||||
;
|
||||
; LP64-LP64F-LP64D-FPELIM-LABEL: va_large_stack:
|
||||
@ -1943,7 +1926,6 @@ define i32 @va_large_stack(i8* %fmt, ...) {
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 0
|
||||
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
|
||||
;
|
||||
; LP64-LP64F-LP64D-WITHFP-LABEL: va_large_stack:
|
||||
@ -1977,12 +1959,8 @@ define i32 @va_large_stack(i8* %fmt, ...) {
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 1952(sp)
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa sp, 1968
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 1960(sp)
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore ra
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore s0
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 2032
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 0
|
||||
; LP64-LP64F-LP64D-WITHFP-NEXT: ret
|
||||
%large = alloca [ 100000000 x i8 ]
|
||||
%va = alloca i8*, align 4
|
||||
|
||||
@ -12,14 +12,13 @@
|
||||
; RELAX: 0x20 R_RISCV_ADD32
|
||||
; RELAX: 0x20 R_RISCV_SUB32
|
||||
; RELAX-NOT: {{[}]}}
|
||||
; RELAX: 0x25 R_RISCV_SET6
|
||||
; RELAX: 0x25 R_RISCV_SUB6
|
||||
; RELAX: 0x39 R_RISCV_SET6
|
||||
; RELAX: 0x39 R_RISCV_SUB6
|
||||
;
|
||||
; RELAX-DWARFDUMP: CIE
|
||||
; RELAX-DWARFDUMP: DW_CFA_advance_loc
|
||||
; RELAX-DWARFDUMP: DW_CFA_def_cfa_offset
|
||||
; RELAX-DWARFDUMP: DW_CFA_offset
|
||||
; RELAX-DWARFDUMP: DW_CFA_restore
|
||||
source_filename = "frame.c"
|
||||
|
||||
; Function Attrs: noinline nounwind optnone
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user