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This CL changes the function prologue and epilogue emitted on X86 when stack needs realignment.
It is intended to fix PR11468. Old prologue and epilogue looked like this: push %rbp mov %rsp, %rbp and $alignment, %rsp push %r14 push %r15 ... pop %r15 pop %r14 mov %rbp, %rsp pop %rbp The problem was to reference the locations of callee-saved registers in exception handling: locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would take some effort to implement this in LLVM, as currently MachineLocation can only have the form "Register + Offset". Funciton prologue and epilogue are now changed to: push %rbp mov %rsp, %rbp push %14 push %15 and $alignment, %rsp ... lea -$size_of_saved_registers(%rbp), %rsp pop %r15 pop %r14 pop %rbp Reviewed by Chad Rosier. llvm-svn: 160248
This commit is contained in:
Alexey Samsonov
parent
0e3ed1b1f3
commit
c68bb48704
@ -722,10 +722,14 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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if (HasFP) {
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// Calculate required stack adjustment.
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uint64_t FrameSize = StackSize - SlotSize;
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if (RegInfo->needsStackRealignment(MF))
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FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
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NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
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if (RegInfo->needsStackRealignment(MF)) {
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// Callee-saved registers are pushed on stack before the stack
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// is realigned.
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FrameSize -= X86FI->getCalleeSavedFrameSize();
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NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
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} else {
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NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
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}
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// Get the offset of the stack slot for the EBP register, which is
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// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
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@ -782,19 +786,6 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
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I != E; ++I)
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I->addLiveIn(FramePtr);
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// Realign stack
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if (RegInfo->needsStackRealignment(MF)) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL,
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TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
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.addReg(StackPtr)
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.addImm(-MaxAlign)
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.setMIFlag(MachineInstr::FrameSetup);
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// The EFLAGS implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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} else {
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NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
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}
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@ -824,6 +815,27 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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}
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// Realign stack after we pushed callee-saved registers (so that we'll be
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// able to calculate their offsets from the frame pointer).
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// NOTE: We push the registers before realigning the stack, so
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// vector callee-saved (xmm) registers may be saved w/o proper
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// alignment in this way. However, currently these regs are saved in
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// stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
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// this shouldn't be a problem.
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if (RegInfo->needsStackRealignment(MF)) {
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assert(HasFP && "There should be a frame pointer if stack is realigned.");
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL,
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TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
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.addReg(StackPtr)
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.addImm(-MaxAlign)
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.setMIFlag(MachineInstr::FrameSetup);
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// The EFLAGS implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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DL = MBB.findDebugLoc(MBBI);
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// If there is an SUB32ri of ESP immediately before this instruction, merge
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@ -975,7 +987,6 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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unsigned SlotSize = RegInfo->getSlotSize();
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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unsigned StackPtr = RegInfo->getStackRegister();
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unsigned BasePtr = RegInfo->getBaseRegister();
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switch (RetOpcode) {
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default:
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@ -1013,10 +1024,14 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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if (hasFP(MF)) {
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// Calculate required stack adjustment.
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uint64_t FrameSize = StackSize - SlotSize;
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if (RegInfo->needsStackRealignment(MF))
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FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
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NumBytes = FrameSize - CSSize;
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if (RegInfo->needsStackRealignment(MF)) {
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// Callee-saved registers were pushed on stack before the stack
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// was realigned.
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FrameSize -= CSSize;
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NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
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} else {
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NumBytes = FrameSize - CSSize;
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}
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// Pop EBP.
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BuildMI(MBB, MBBI, DL,
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@ -1026,7 +1041,6 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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}
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// Skip the callee-saved pop instructions.
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MachineBasicBlock::iterator LastCSPop = MBBI;
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while (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PI = prior(MBBI);
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unsigned Opc = PI->getOpcode();
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@ -1037,6 +1051,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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--MBBI;
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}
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MachineBasicBlock::iterator FirstCSPop = MBBI;
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DL = MBBI->getDebugLoc();
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@ -1045,40 +1060,19 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
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if (NumBytes || MFI->hasVarSizedObjects())
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mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
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// Restore the SP from the BP, if necessary.
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if (RegInfo->hasBasePointer(MF)) {
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BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
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StackPtr).addReg(BasePtr);
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// When restoring from the BP we must use a cached SP adjustment.
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NumBytes = X86FI->getBasePtrStackAdjustment();
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}
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// If dynamic alloca is used, then reset esp to point to the last callee-saved
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// slot before popping them off! Same applies for the case, when stack was
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// realigned.
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if (RegInfo->needsStackRealignment(MF)) {
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// We cannot use LEA here, because stack pointer was realigned. We need to
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// deallocate local frame back.
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if (CSSize) {
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emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII,
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*RegInfo);
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MBBI = prior(LastCSPop);
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}
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BuildMI(MBB, MBBI, DL,
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TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
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StackPtr).addReg(FramePtr);
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} else if (MFI->hasVarSizedObjects()) {
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if (CSSize) {
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unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
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MachineInstr *MI =
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addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
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FramePtr, false, -CSSize);
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MBB.insert(MBBI, MI);
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if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
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if (RegInfo->needsStackRealignment(MF))
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MBBI = FirstCSPop;
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if (CSSize != 0) {
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unsigned Opc = getLEArOpcode(Is64Bit);
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addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
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FramePtr, false, -CSSize);
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} else {
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BuildMI(MBB, MBBI, DL,
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TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
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unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
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BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
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.addReg(FramePtr);
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}
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} else if (NumBytes) {
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@ -85,20 +85,19 @@ entry:
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; CHECK: _t4
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK: andq $-32, %rsp
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; CHECK: pushq %r14
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; CHECK: pushq %rbx
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; CHECK: subq $[[STACKADJ:[0-9]+]], %rsp
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; CHECK: andq $-32, %rsp
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; CHECK: subq ${{[0-9]+}}, %rsp
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; CHECK: movq %rsp, %rbx
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;
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; CHECK: leaq {{[0-9]*}}(%rbx), %rdi
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; CHECK: leaq {{[0-9]*}}(%rbx), %rdx
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; CHECK: callq _t4_helper
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;
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; CHECK: addq $[[STACKADJ]], %rsp
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; CHECK: leaq -16(%rbp), %rsp
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; CHECK: popq %rbx
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; CHECK: popq %r14
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; CHECK: movq %rbp, %rsp
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; CHECK: popq %rbp
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}
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@ -176,19 +175,17 @@ entry:
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; CHECK: _t7
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK: andq $-32, %rsp
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; CHECK: pushq %rbx
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; CHECK: subq $[[ADJ:[0-9]+]], %rsp
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; CHECK: andq $-32, %rsp
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; CHECK: subq ${{[0-9]+}}, %rsp
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; CHECK: movq %rsp, %rbx
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; Stack adjustment for byval
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; CHECK: subq {{.*}}, %rsp
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; CHECK: callq _bar
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; CHECK-NOT: addq {{.*}}, %rsp
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; CHECK: movq %rbx, %rsp
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; CHECK: addq $[[ADJ]], %rsp
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; CHECK: leaq -8(%rbp), %rsp
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; CHECK: popq %rbx
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; CHECK: movq %rbp, %rsp
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; CHECK: popq %rbp
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}
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@ -229,14 +226,12 @@ entry:
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; FORCE-ALIGN: _t9
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; FORCE-ALIGN: pushq %rbp
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; FORCE-ALIGN: movq %rsp, %rbp
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; FORCE-ALIGN: andq $-32, %rsp
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; FORCE-ALIGN: pushq %rbx
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; FORCE-ALIGN: subq $24, %rsp
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; FORCE-ALIGN: andq $-32, %rsp
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; FORCE-ALIGN: subq $32, %rsp
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; FORCE-ALIGN: movq %rsp, %rbx
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; FORCE-ALIGN: movq %rbx, %rsp
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; FORCE-ALIGN: addq $24, %rsp
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; FORCE-ALIGN: leaq -8(%rbp), %rsp
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; FORCE-ALIGN: popq %rbx
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; FORCE-ALIGN: movq %rbp, %rsp
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; FORCE-ALIGN: popq %rbp
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}
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@ -19,10 +19,10 @@ define i64 @g(i32 %i) nounwind {
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; CHECK: g:
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; CHECK: pushl %ebp
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; CHECK-NEXT: movl %esp, %ebp
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; CHECK-NEXT: pushl
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; CHECK-NEXT: pushl
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; CHECK-NEXT: andl $-32, %esp
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; CHECK-NEXT: pushl
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; CHECK-NEXT: pushl
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; CHECK-NEXT: subl $24, %esp
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; CHECK-NEXT: subl $32, %esp
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;
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; Now setup the base pointer (%ebx).
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; CHECK-NEXT: movl %esp, %ebx
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@ -46,17 +46,13 @@ define i64 @g(i32 %i) nounwind {
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; CHECK-NEXT: addl $32, %esp
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; CHECK-NOT: {{[^ ,]*}}, %esp
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;
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; Restore %esp from %ebx (base pointer) so we can pop the callee-saved
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; registers. This is the state prior to the allocation of VLAs.
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; Restore %esp from %ebp (frame pointer) and subtract the size of
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; zone with callee-saved registers to pop them.
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; This is the state prior to stack realignment and the allocation of VLAs.
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; CHECK-NOT: popl
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; CHECK: movl %ebx, %esp
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; CHECK-NEXT: addl $24, %esp
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; CHECK: leal -8(%ebp), %esp
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; CHECK-NEXT: popl
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; CHECK-NEXT: popl
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;
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; Finally we need to restore %esp from %ebp due to dynamic stack
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; realignment.
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; CHECK-NEXT: movl %ebp, %esp
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; CHECK-NEXT: popl %ebp
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; CHECK-NEXT: ret
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33
test/CodeGen/X86/pr11468.ll
Normal file
33
test/CodeGen/X86/pr11468.ll
Normal file
@ -0,0 +1,33 @@
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; RUN: llc < %s -force-align-stack -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s
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; PR11468
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define void @f(i64 %sz) uwtable {
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entry:
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%a = alloca i32, align 32
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store volatile i32 0, i32* %a, align 32
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; force to push r14 on stack
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call void asm sideeffect "nop", "~{r14},~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0
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ret void
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; CHECK: _f
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; CHECK: pushq %rbp
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; CHECK: .cfi_offset %rbp, -16
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; CHECK: movq %rsp, %rbp
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; CHECK: .cfi_def_cfa_register %rbp
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; We first push register on stack, and then realign it, so that
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; .cfi_offset value is correct
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; CHECK: pushq %r14
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; CHECK: andq $-32, %rsp
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; CHECK: .cfi_offset %r14, -24
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; Restore %rsp from %rbp and subtract the total size of saved regsiters.
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; CHECK: leaq -8(%rbp), %rsp
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; Pop saved registers.
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; CHECK: popq %r14
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; CHECK: popq %rbp
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}
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!0 = metadata !{i32 125}
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