From c68f12ff30a55bc2ffbc1ce99ec14d97dd943083 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 13 Jul 2011 23:22:26 +0000 Subject: [PATCH] Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106 --- include/llvm/MC/MCInstrDesc.h | 7 + include/llvm/Target/Target.td | 7 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 20 +-- lib/Target/ARM/ARMBaseInstrInfo.h | 18 +-- lib/Target/ARM/ARMInstrFormats.td | 209 +++++++++++++--------------- lib/Target/ARM/ARMInstrInfo.td | 112 +++++++-------- lib/Target/ARM/ARMInstrThumb.td | 34 ++--- lib/Target/ARM/ARMInstrThumb2.td | 50 +++---- lib/Target/ARM/ARMInstrVFP.td | 4 +- lib/Target/ARM/ARMMCCodeEmitter.cpp | 12 +- utils/TableGen/InstrInfoEmitter.cpp | 6 +- 11 files changed, 230 insertions(+), 249 deletions(-) diff --git a/include/llvm/MC/MCInstrDesc.h b/include/llvm/MC/MCInstrDesc.h index 17d5fdc5d3d..c7a7235b051 100644 --- a/include/llvm/MC/MCInstrDesc.h +++ b/include/llvm/MC/MCInstrDesc.h @@ -122,6 +122,7 @@ public: unsigned short NumOperands; // Num of args (may be more if variable_ops) unsigned short NumDefs; // Num of args that are definitions unsigned short SchedClass; // enum identifying instr sched class + unsigned short Size; // Number of bytes in encoding. const char * Name; // Name of the instruction record in td file unsigned Flags; // Flags identifying machine instr class uint64_t TSFlags; // Target Specific Flag values @@ -255,6 +256,12 @@ public: return SchedClass; } + /// getSize - Return the number of bytes in the encoding of this instruction, + /// or zero if the encoding size cannot be known from the opcode. + unsigned getSize() const { + return Size; + } + bool isReturn() const { return Flags & (1 << MCID::Return); } diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index ebe962bbc42..360eea3dd6b 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -293,7 +293,12 @@ class Instruction { // code. list Predicates = []; - // Code size. + // Size - Size of encoded instruction, or zero if the size cannot be determined + // from the opcode. + int Size = 0; + + // Code size, for instruction selection. + // FIXME: What does this actually mean? int CodeSize = 0; // Added complexity passed onto matching pattern. diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index b1aa7ce4b6c..2c5212aed0e 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -529,35 +529,23 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { const MachineFunction *MF = MBB.getParent(); const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); - // Basic size info comes from the TSFlags field. const MCInstrDesc &MCID = MI->getDesc(); - uint64_t TSFlags = MCID.TSFlags; + if (MCID.getSize()) + return MCID.getSize(); - unsigned Opc = MI->getOpcode(); - switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { - default: { // If this machine instr is an inline asm, measure it. if (MI->getOpcode() == ARM::INLINEASM) return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI); if (MI->isLabel()) return 0; + unsigned Opc = MI->getOpcode(); switch (Opc) { - default: - llvm_unreachable("Unknown or unset size field for instr!"); case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: case TargetOpcode::PROLOG_LABEL: case TargetOpcode::EH_LABEL: case TargetOpcode::DBG_VALUE: return 0; - } - break; - } - case ARMII::Size8Bytes: return 8; // ARM instruction x 2. - case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. - case ARMII::Size2Bytes: return 2; // Thumb1 instruction. - case ARMII::SizeSpecial: { - switch (Opc) { case ARM::MOVi16_ga_pcrel: case ARM::MOVTi16_ga_pcrel: case ARM::t2MOVi16_ga_pcrel: @@ -621,8 +609,6 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { // Otherwise, pseudo-instruction sizes are zero. return 0; } - } - } return 0; // Not reached } diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index 1d8799fd668..507e8974bf7 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -39,24 +39,16 @@ namespace ARMII { // This four-bit field describes the addressing mode used. AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h - // Size* - Flags to keep track of the size of an instruction. - SizeShift = 5, - SizeMask = 7 << SizeShift, - SizeSpecial = 1, // 0 byte pseudo or special case. - Size8Bytes = 2, - Size4Bytes = 3, - Size2Bytes = 4, - // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load // and store ops only. Generic "updating" flag is used for ld/st multiple. // The index mode enums are declared in ARMBaseInfo.h - IndexModeShift = 8, + IndexModeShift = 5, IndexModeMask = 3 << IndexModeShift, //===------------------------------------------------------------------===// // Instruction encoding formats. // - FormShift = 10, + FormShift = 7, FormMask = 0x3f << FormShift, // Pseudo instructions @@ -129,15 +121,15 @@ namespace ARMII { // UnaryDP - Indicates this is a unary data processing instruction, i.e. // it doesn't have a Rn operand. - UnaryDP = 1 << 16, + UnaryDP = 1 << 13, // Xform16Bit - Indicates this Thumb2 instruction may be transformed into // a 16-bit Thumb instruction if certain conditions are met. - Xform16Bit = 1 << 17, + Xform16Bit = 1 << 14, //===------------------------------------------------------------------===// // Code domain. - DomainShift = 18, + DomainShift = 15, DomainMask = 7 << DomainShift, DomainGeneral = 0 << DomainShift, DomainVFP = 1 << DomainShift, diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 45bbcd88cbd..3ccf22f80b7 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -107,16 +107,6 @@ def AddrModeT2_pc : AddrMode<14>; def AddrModeT2_i8s4 : AddrMode<15>; def AddrMode_i12 : AddrMode<16>; -// Instruction size. -class SizeFlagVal val> { - bits<3> Value = val; -} -def SizeInvalid : SizeFlagVal<0>; // Unset. -def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. -def Size8Bytes : SizeFlagVal<2>; -def Size4Bytes : SizeFlagVal<3>; -def Size2Bytes : SizeFlagVal<4>; - // Load / store index mode. class IndexMode val> { bits<2> Value = val; @@ -236,13 +226,13 @@ def shr_imm64 : Operand { // ARM Instruction templates. // -class InstTemplate : Instruction { let Namespace = "ARM"; AddrMode AM = am; - SizeFlagVal SZ = sz; + int Size = sz; IndexMode IM = im; bits<2> IndexModeBits = IM.Value; Format F = f; @@ -256,12 +246,11 @@ class InstTemplate Inst; } -class InstARM : InstTemplate, Encoding; // This Encoding-less class is used by Thumb1 to specify the encoding bits later // on by adding flavors to specific instructions. -class InstThumb : InstTemplate; class PseudoInst pattern> - : InstTemplate { let OutOperandList = oops; let InOperandList = iops; @@ -292,49 +281,49 @@ class PseudoInst pattern> } // PseudoInst that's ARM-mode only. -class ARMPseudoInst pattern> : PseudoInst { - let SZ = sz; + let Size = sz; list Predicates = [IsARM]; } // PseudoInst that's Thumb-mode only. -class tPseudoInst pattern> : PseudoInst { - let SZ = sz; + let Size = sz; list Predicates = [IsThumb]; } // PseudoInst that's Thumb2-mode only. -class t2PseudoInst pattern> : PseudoInst { - let SZ = sz; + let Size = sz; list Predicates = [IsThumb2]; } -class ARMPseudoExpand pattern, dag Result> : ARMPseudoInst, PseudoInstExpansion; -class tPseudoExpand pattern, dag Result> : tPseudoInst, PseudoInstExpansion; -class t2PseudoExpand pattern, dag Result> : t2PseudoInst, PseudoInstExpansion; // Almost all ARM instructions are predicable. -class I pattern> @@ -349,7 +338,7 @@ class I pattern> @@ -365,7 +354,7 @@ class InoP pattern> @@ -383,7 +372,7 @@ class sI pattern> : InstARM { @@ -396,31 +385,31 @@ class XI pattern> - : I; class AsI pattern> - : sI; class AXI pattern> - : XI; class AInoP pattern> - : InoP; // Ctrl flow instructions class ABI opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { let Inst{27-24} = opcod; } class ABXI opcod, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> - : XI { let Inst{27-24} = opcod; } @@ -428,13 +417,13 @@ class ABXI opcod, dag oops, dag iops, InstrItinClass itin, // BR_JT instructions class JTI pattern> - : XI; // Atomic load/store instructions class AIldrex opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<4> Rt; bits<4> Rn; @@ -447,7 +436,7 @@ class AIldrex opcod, dag oops, dag iops, InstrItinClass itin, } class AIstrex opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<4> Rd; bits<4> Rt; @@ -477,21 +466,21 @@ class AIswp pattern> // addrmode1 instructions class AI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> - : I { let Inst{24-21} = opcod; let Inst{27-26} = 0b00; } class AsI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> - : sI { let Inst{24-21} = opcod; let Inst{27-26} = 0b00; } class AXI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string asm, list pattern> - : XI { let Inst{24-21} = opcod; let Inst{27-26} = 0b00; @@ -503,7 +492,7 @@ class AXI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, class AI2ldst op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin, string opc, string asm, list pattern> - : I { let Inst{27-25} = op; let Inst{24} = 1; // 24 == P @@ -516,7 +505,7 @@ class AI2ldst op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, class AI2ldstidx pattern> - : I { bits<4> Rt; let Inst{27-26} = 0b01; @@ -564,7 +553,7 @@ class AI2stridxT op, bit op20, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<14> addr; bits<4> Rt; @@ -584,7 +573,7 @@ class AI3ld op, bit op20, dag oops, dag iops, Format f, class AI3ldstidx op, bit op20, bit isLd, bit isPre, dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, string opc, string asm, string cstr, list pattern> - : I { bits<4> Rt; let Inst{27-25} = 0b000; @@ -600,7 +589,7 @@ class AI3ldstidx op, bit op20, bit isLd, bit isPre, dag oops, dag iops, class AI3ldstidxT op, bit op20, bit isLd, bit isPre, dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, string opc, string asm, string cstr, list pattern> - : I { // {13} 1 == imm8, 0 == Rm // {12-9} Rn @@ -644,7 +633,7 @@ class AI3stridx op, bit isByte, bit isPre, dag oops, dag iops, // stores class AI3str op, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<14> addr; bits<4> Rt; @@ -664,7 +653,7 @@ class AI3str op, dag oops, dag iops, Format f, InstrItinClass itin, // Pre-indexed stores class AI3sthpr pattern> - : I { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -677,7 +666,7 @@ class AI3sthpr pattern> - : I { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -692,7 +681,7 @@ class AI3stdpr pattern> - : I { // {13} 1 == imm8, 0 == Rm // {12-9} Rn @@ -718,7 +707,7 @@ class AI3sthpo pattern> - : I { let Inst{4} = 1; let Inst{5} = 1; // H bit @@ -733,7 +722,7 @@ class AI3stdpo pattern> - : XI { + : XI { bits<4> p; bits<16> regs; bits<4> Rn; @@ -747,7 +736,7 @@ class AXI4 opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { let Inst{7-4} = 0b1001; let Inst{20} = 0; // S bit @@ -755,7 +744,7 @@ class AMul1I opcod, dag oops, dag iops, InstrItinClass itin, } class AsMul1I opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : sI { let Inst{7-4} = 0b1001; let Inst{27-21} = opcod; @@ -764,7 +753,7 @@ class AsMul1I opcod, dag oops, dag iops, InstrItinClass itin, // Most significant word multiply class AMul2I opcod, bits<4> opc7_4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<4> Rd; bits<4> Rn; @@ -787,7 +776,7 @@ class AMul2Ia opcod, bits<4> opc7_4, dag oops, dag iops, // SMUL / SMULW / SMLA / SMLAW class AMulxyIbase opcod, bits<2> bit6_5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<4> Rn; bits<4> Rm; @@ -826,7 +815,7 @@ class AMulxyI64 opcod, bits<2> bit6_5, dag oops, dag iops, // Extend instructions. class AExtI opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { // All AExtI instructions have Rd and Rm register operands. bits<4> Rd; @@ -841,7 +830,7 @@ class AExtI opcod, dag oops, dag iops, InstrItinClass itin, // Misc Arithmetic instructions. class AMiscA1I opcod, bits<4> opc7_4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<4> Rd; bits<4> Rm; @@ -856,7 +845,7 @@ class AMiscA1I opcod, bits<4> opc7_4, dag oops, dag iops, // PKH instructions class APKHI opcod, bit tb, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : I { bits<4> Rd; bits<4> Rn; @@ -891,7 +880,7 @@ class ARMV6Pat : Pat { // Thumb Instruction Format Definitions. // -class ThumbI pattern> : InstThumb { let OutOperandList = oops; @@ -903,19 +892,19 @@ class ThumbI pattern> - : ThumbI; + : ThumbI; // Two-address instructions class TIt pattern> - : ThumbI; // tBL, tBX 32-bit instructions class TIx2 opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> - : ThumbI, + : ThumbI, Encoding { let Inst{31-27} = opcod1; let Inst{15-14} = opcod2; @@ -925,10 +914,10 @@ class TIx2 opcod1, bits<2> opcod2, bit opcod3, // BR_JT instructions class TJTI pattern> - : ThumbI; + : ThumbI; // Thumb1 only -class Thumb1I pattern> : InstThumb { let OutOperandList = oops; @@ -940,19 +929,19 @@ class Thumb1I pattern> - : Thumb1I; + : Thumb1I; class T1Ix2 pattern> - : Thumb1I; + : Thumb1I; // Two-address instructions class T1It pattern> - : Thumb1I; // Thumb1 instruction that can either be predicated or set CPSR. -class Thumb1sI pattern> : InstThumb { @@ -965,16 +954,16 @@ class Thumb1sI pattern> - : Thumb1sI; + : Thumb1sI; // Two-address instructions class T1sIt pattern> - : Thumb1sI; // Thumb1 instruction that can be predicated. -class Thumb1pI pattern> : InstThumb { @@ -987,17 +976,17 @@ class Thumb1pI pattern> - : Thumb1pI; + : Thumb1pI; // Two-address instructions class T1pIt pattern> - : Thumb1pI; class T1pIs pattern> - : Thumb1pI; + : Thumb1pI; class Encoding16 : Encoding { let Inst{31-16} = 0x0000; @@ -1046,7 +1035,7 @@ class T1BranchCond opcode> : Encoding16 { class T1pILdStEncode opcode, dag oops, dag iops, AddrMode am, InstrItinClass itin, string opc, string asm, list pattern> - : Thumb1pI, + : Thumb1pI, T1LoadStore<0b0101, opcode> { bits<3> Rt; bits<8> addr; @@ -1057,7 +1046,7 @@ class T1pILdStEncode opcode, dag oops, dag iops, AddrMode am, class T1pILdStEncodeImm opA, bit opB, dag oops, dag iops, AddrMode am, InstrItinClass itin, string opc, string asm, list pattern> - : Thumb1pI, + : Thumb1pI, T1LoadStore { bits<3> Rt; bits<8> addr; @@ -1073,7 +1062,7 @@ class T1Misc opcode> : Encoding16 { } // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. -class Thumb2I pattern> : InstARM { @@ -1090,7 +1079,7 @@ class Thumb2I pattern> : InstARM { @@ -1105,7 +1094,7 @@ class Thumb2sI pattern> : InstARM { @@ -1116,7 +1105,7 @@ class Thumb2XI Predicates = [IsThumb2]; } -class ThumbXI pattern> : InstARM { @@ -1129,22 +1118,22 @@ class ThumbXI pattern> - : Thumb2I; + : Thumb2I; class T2Ii12 pattern> - : Thumb2I; + : Thumb2I; class T2Ii8 pattern> - : Thumb2I; + : Thumb2I; class T2Iso pattern> - : Thumb2I; + : Thumb2I; class T2Ipc pattern> - : Thumb2I; + : Thumb2I; class T2Ii8s4 pattern> - : Thumb2I { bits<4> Rt; bits<4> Rt2; @@ -1163,14 +1152,14 @@ class T2Ii8s4 pattern> - : Thumb2sI; + : Thumb2sI; class T2XI pattern> - : Thumb2XI; + : Thumb2XI; class T2JTI pattern> - : Thumb2XI; + : Thumb2XI; // Move to/from coprocessor instructions class T2Cop opc, dag oops, dag iops, string asm, list pattern> @@ -1181,14 +1170,14 @@ class T2Cop opc, dag oops, dag iops, string asm, list pattern> // Two-address instructions class T2XIt pattern> - : Thumb2XI; + : Thumb2XI; // T2Iidxldst - Thumb2 indexed load / store instructions. class T2Iidxldst opcod, bit load, bit pre, dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, string opc, string asm, string cstr, list pattern> - : InstARM { + : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", asm); @@ -1242,7 +1231,7 @@ class T2Pat : Pat { // // Almost all VFP instructions are predicable. -class VFPI pattern> : InstARM { @@ -1257,7 +1246,7 @@ class VFPI pattern> : InstARM { @@ -1273,7 +1262,7 @@ class VFPXI pattern> - : VFPI { let PostEncoderMethod = "VFPThumb2PostEncoder"; } @@ -1282,7 +1271,7 @@ class VFPAI opcod1, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : VFPI { // Instruction operands. bits<5> Dd; @@ -1308,7 +1297,7 @@ class ADI5 opcod1, bits<2> opcod2, dag oops, dag iops, class ASI5 opcod1, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> - : VFPI { // Instruction operands. bits<5> Sd; @@ -1334,7 +1323,7 @@ class ASI5 opcod1, bits<2> opcod2, dag oops, dag iops, // VFP Load / store multiple pseudo instructions. class PseudoVFPLdStM pattern> - : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); @@ -1345,7 +1334,7 @@ class PseudoVFPLdStM pattern> - : VFPXI { // Instruction operands. bits<4> Rn; @@ -1365,7 +1354,7 @@ class AXDI4 pattern> - : VFPXI { // Instruction operands. bits<4> Rn; @@ -1579,7 +1568,7 @@ class AVConv5I opcod1, bits<4> opcod2, dag oops, dag iops, class NeonI pattern> - : InstARM { + : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); @@ -1591,7 +1580,7 @@ class NeonI pattern> - : InstARM { + : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", "\t", asm); @@ -1631,7 +1620,7 @@ class NLdStLn op21_20, bits<4> op11_8, bits<4> op7_4, } class PseudoNLdSt - : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); @@ -1640,7 +1629,7 @@ class PseudoNLdSt class PseudoNeonI pattern> - : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); @@ -1869,7 +1858,7 @@ class N3VX op21_20, bits<4> op11_8, bit op6, class NVLaneOp opcod1, bits<4> opcod2, bits<2> opcod3, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, list pattern> - : InstARM { let Inst{27-20} = opcod1; let Inst{11-8} = opcod2; diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 437f964a5cd..452f9081e72 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1034,15 +1034,15 @@ multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode, let usesCustomInserter = 1 in { multiclass AI1_adde_sube_s_irs { def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), - Size4Bytes, IIC_iALUi, + 4, IIC_iALUi, [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>; def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), - Size4Bytes, IIC_iALUr, + 4, IIC_iALUr, [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { let isCommutable = Commutable; } def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), - Size4Bytes, IIC_iALUsr, + 4, IIC_iALUsr, [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>; } } @@ -1301,40 +1301,40 @@ def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, // Address computation and loads and stores in PIC mode. let isNotDuplicable = 1 in { def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), - Size4Bytes, IIC_iALUr, + 4, IIC_iALUr, [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; let AddedComplexity = 10 in { def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iLoad_r, + 4, IIC_iLoad_r, [(set GPR:$dst, (load addrmodepc:$addr))]>; def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iLoad_bh_r, + 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iLoad_bh_r, + 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iLoad_bh_r, + 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iLoad_bh_r, + 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; } let AddedComplexity = 10 in { def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; + 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, + 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), - Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; + 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; } } // isNotDuplicable = 1 @@ -1356,11 +1356,11 @@ def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), let Inst{11-0} = label; } def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), - Size4Bytes, IIC_iALUi, []>; + 4, IIC_iALUi, []>; def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, nohash_imm:$id, pred:$p), - Size4Bytes, IIC_iALUi, []>; + 4, IIC_iALUi, []>; //===----------------------------------------------------------------------===// // Control Flow Instructions. @@ -1451,12 +1451,12 @@ let isCall = 1, // ARMv4T // Note: Restrict $func to the tGPR regclass to prevent it being in LR. def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), - Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, + 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsARM, HasV4T, IsNotDarwin]>; // ARMv4 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), - Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, + 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsARM, NoV4T, IsNotDarwin]>; } @@ -1467,26 +1467,26 @@ let isCall = 1, Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR], Uses = [R7, SP] in { def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops), - Size4Bytes, IIC_Br, + 4, IIC_Br, [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>, Requires<[IsARM, IsDarwin]>; def BLr9_pred : ARMPseudoExpand<(outs), (ins bl_target:$func, pred:$p, variable_ops), - Size4Bytes, IIC_Br, + 4, IIC_Br, [(ARMcall_pred tglobaladdr:$func)], (BL_pred bl_target:$func, pred:$p)>, Requires<[IsARM, IsDarwin]>; // ARMv5T and above def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops), - Size4Bytes, IIC_Br, + 4, IIC_Br, [(ARMcall GPR:$func)], (BLX GPR:$func)>, Requires<[IsARM, HasV5T, IsDarwin]>; def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops), - Size4Bytes, IIC_Br, + 4, IIC_Br, [(ARMcall_pred GPR:$func)], (BLX_pred GPR:$func, pred:$p)>, Requires<[IsARM, HasV5T, IsDarwin]>; @@ -1494,12 +1494,12 @@ let isCall = 1, // ARMv4T // Note: Restrict $func to the tGPR regclass to prevent it being in LR. def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), - Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, + 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsARM, HasV4T, IsDarwin]>; // ARMv4 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), - Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, + 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsARM, NoV4T, IsDarwin]>; } @@ -1519,24 +1519,24 @@ let isBranch = 1, isTerminator = 1 in { // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly // should be sufficient. // FIXME: Is B really a Barrier? That doesn't seem right. - def B : ARMPseudoExpand<(outs), (ins br_target:$target), Size4Bytes, IIC_Br, + def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>; let isNotDuplicable = 1, isIndirectBranch = 1 in { def BR_JTr : ARMPseudoInst<(outs), (ins GPR:$target, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, + 0, IIC_Br, [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; // FIXME: This shouldn't use the generic "addrmode2," but rather be split // into i12 and rs suffixed versions. def BR_JTm : ARMPseudoInst<(outs), (ins addrmode2:$target, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, + 0, IIC_Br, [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, imm:$id)]>; def BR_JTadd : ARMPseudoInst<(outs), (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, + 0, IIC_Br, [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>; } // isNotDuplicable = 1, isIndirectBranch = 1 @@ -1577,12 +1577,12 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { IIC_Br, []>, Requires<[IsDarwin]>; def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (Bcc br_target:$dst, (ops 14, zero_reg))>, Requires<[IsARM, IsDarwin]>; def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (BX GPR:$dst)>, Requires<[IsARM, IsDarwin]>; @@ -1598,12 +1598,12 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { IIC_Br, []>, Requires<[IsNotDarwin]>; def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (Bcc br_target:$dst, (ops 14, zero_reg))>, Requires<[IsARM, IsNotDarwin]>; def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (BX GPR:$dst)>, Requires<[IsARM, IsNotDarwin]>; } @@ -2063,7 +2063,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), - Size4Bytes, IIC_iLoad_mBr, [], + 4, IIC_iLoad_mBr, [], (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, RegConstraint<"$Rn = $wb">; @@ -2234,7 +2234,7 @@ defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; def SBFX : I<(outs GPR:$Rd), (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width), - AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, + AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; @@ -2251,7 +2251,7 @@ def SBFX : I<(outs GPR:$Rd), def UBFX : I<(outs GPR:$Rd), (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width), - AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, + AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; @@ -2343,13 +2343,13 @@ def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), // NOTE: CPSR def omitted because it will be handled by the custom inserter. let usesCustomInserter = 1 in { def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), - Size4Bytes, IIC_iALUi, + 4, IIC_iALUi, [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>; def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), - Size4Bytes, IIC_iALUr, + 4, IIC_iALUr, [/* For disassembly only; pattern left blank */]>; def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), - Size4Bytes, IIC_iALUsr, + 4, IIC_iALUsr, [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>; } @@ -2397,10 +2397,10 @@ def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), // NOTE: CPSR def omitted because it will be handled by the custom inserter. let usesCustomInserter = 1, Uses = [CPSR] in { def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), - Size4Bytes, IIC_iALUi, + 4, IIC_iALUi, [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>; def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), - Size4Bytes, IIC_iALUsr, + 4, IIC_iALUsr, [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>; } @@ -2612,7 +2612,7 @@ defm BIC : AsI1_bin_irs<0b1110, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">; def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), - AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, + AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "bfc", "\t$Rd, $imm", "$src = $Rd", [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, Requires<[IsARM, HasV6T2]> { @@ -2627,7 +2627,7 @@ def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), // A8.6.18 BFI - Bitfield insert (Encoding A1) def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm), - AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, + AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm))]>, @@ -2647,7 +2647,7 @@ def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm), let isAsmParserOnly = 1 in def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, lsb_pos_imm:$lsb, width_imm:$width), - AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, + AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd", []>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; @@ -2738,7 +2738,7 @@ def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), let Constraints = "@earlyclobber $Rd" in def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMUL32, + 4, IIC_iMUL32, [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))], (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; @@ -2755,7 +2755,7 @@ def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), let Constraints = "@earlyclobber $Rd" in def MLAv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMAC32, + 4, IIC_iMAC32, [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))], (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; @@ -2790,13 +2790,13 @@ def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMUL64, [], + 4, IIC_iMUL64, [], (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMUL64, [], + 4, IIC_iMUL64, [], (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; } @@ -2829,17 +2829,17 @@ def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMAC64, [], + 4, IIC_iMAC64, [], (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), - Size4Bytes, IIC_iMAC64, [], + 4, IIC_iMAC64, [], (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>; def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p), - Size4Bytes, IIC_iMAC64, [], + 4, IIC_iMAC64, [], (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>, Requires<[IsARM, NoV6]>; } @@ -3247,26 +3247,26 @@ def BCCZi64 : PseudoInst<(outs), // a two-value operand where a dag node expects two operands. :( let neverHasSideEffects = 1 in { def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p), - Size4Bytes, IIC_iCMOVr, + 4, IIC_iCMOVr, [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $Rd">; def MOVCCs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, so_reg:$shift, pred:$p), - Size4Bytes, IIC_iCMOVsr, + 4, IIC_iCMOVsr, [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $Rd">; let isMoveImm = 1 in def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, i32imm_hilo16:$imm, pred:$p), - Size4Bytes, IIC_iMOVi, + 4, IIC_iMOVi, []>, RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; let isMoveImm = 1 in def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, so_imm:$imm, pred:$p), - Size4Bytes, IIC_iCMOVi, + 4, IIC_iCMOVi, [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $Rd">; @@ -3274,12 +3274,12 @@ def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), let isMoveImm = 1 in def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, i32imm:$src, pred:$p), - Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">; + 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">; let isMoveImm = 1 in def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, so_imm:$imm, pred:$p), - Size4Bytes, IIC_iCMOVi, + 4, IIC_iCMOVi, [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $Rd">; } // neverHasSideEffects @@ -3525,7 +3525,7 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, class ACI - : InoP { let Inst{27-25} = 0b110; } @@ -3885,7 +3885,7 @@ def Int_eh_sjlj_dispatchsetup : // ARMv4 indirect branch using (MOVr PC, dst) let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), - Size4Bytes, IIC_Br, [(brind GPR:$dst)], + 4, IIC_Br, [(brind GPR:$dst)], (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, Requires<[IsARM, NoV4T]>; diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index db945b59c33..5870f58baa3 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -369,12 +369,12 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { } let isReturn = 1, isTerminator = 1, isBarrier = 1 in { - def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), Size2Bytes, IIC_Br, + def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, [(ARMretflag)], (tBX LR, pred:$p)>; // Alternative return instruction used by vararg functions. def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), - Size2Bytes, IIC_Br, [], + 2, IIC_Br, [], (tBX GPR:$Rm, pred:$p)>; } @@ -425,7 +425,7 @@ let isCall = 1, // ARMv4T def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), - Size4Bytes, IIC_Br, + 4, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; } @@ -477,7 +477,7 @@ let isCall = 1, // ARMv4T def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops), - Size4Bytes, IIC_Br, + 4, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsThumb, IsThumb1Only, IsDarwin]>; } @@ -496,11 +496,11 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in { // the clobber of LR. let Defs = [LR] in def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target), - Size4Bytes, IIC_Br, [], (tBL t_bltarget:$target)>; + 4, IIC_Br, [], (tBL t_bltarget:$target)>; def tBR_JTr : tPseudoInst<(outs), (ins tGPR:$target, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, + 0, IIC_Br, [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> { list Predicates = [IsThumb, IsThumb1Only]; } @@ -552,7 +552,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls // on Darwin), so it's in ARMInstrThumb2.td. def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (tBX GPR:$dst, (ops 14, zero_reg))>, Requires<[IsThumb, IsDarwin]>; } @@ -560,11 +560,11 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in { def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (tB t_brtarget:$dst)>, Requires<[IsThumb, IsNotDarwin]>; def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (tBX GPR:$dst, (ops 14, zero_reg))>, Requires<[IsThumb, IsNotDarwin]>; } @@ -1049,7 +1049,7 @@ def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, let neverHasSideEffects = 1 in { def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, - Size2Bytes, IIC_iMOVr, + 2, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>, T1Special<{1,0,?,?}> { // A8.6.97 @@ -1223,11 +1223,11 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), let neverHasSideEffects = 1, isReMaterializable = 1 in def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), - Size2Bytes, IIC_iALUi, []>; + 2, IIC_iALUi, []>; def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, nohash_imm:$id, pred:$p), - Size2Bytes, IIC_iALUi, []>; + 2, IIC_iALUi, []>; //===----------------------------------------------------------------------===// // TLS Instructions @@ -1237,7 +1237,7 @@ def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), // This is a pseudo inst so that we can get the encoding right, // complete with fixup for the aeabi_read_tp function. let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in -def tTPsoft : tPseudoInst<(outs), (ins), Size4Bytes, IIC_Br, +def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, [(set R0, ARMthread_pointer)]>; //===----------------------------------------------------------------------===// @@ -1257,14 +1257,14 @@ def tTPsoft : tPseudoInst<(outs), (ins), Size4Bytes, IIC_Br, let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), - AddrModeNone, SizeSpecial, NoItinerary, "","", + AddrModeNone, 0, NoItinerary, "","", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; // FIXME: Non-Darwin version(s) let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, Defs = [ R7, LR, SP ] in def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), - AddrModeNone, SizeSpecial, IndexModeNone, + AddrModeNone, 0, IndexModeNone, Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, Requires<[IsThumb, IsDarwin]>; @@ -1383,12 +1383,12 @@ def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1 in def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), - Size2Bytes, IIC_iPop_Br, [], + 2, IIC_iPop_Br, [], (tPOP pred:$p, reglist:$regs)>; // Indirect branch using "mov pc, $Rm" let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), - Size2Bytes, IIC_Br, [(brind GPR:$Rm)], + 2, IIC_Br, [(brind GPR:$Rm)], (tMOVr PC, GPR:$Rm, pred:$p)>; } diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index eeee0418d8e..e871412275e 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -716,18 +716,18 @@ let usesCustomInserter = 1 in { multiclass T2I_adde_sube_s_irs { // shifted imm def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), - Size4Bytes, IIC_iALUi, + 4, IIC_iALUi, [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>; // register def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), - Size4Bytes, IIC_iALUr, + 4, IIC_iALUr, [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { let isCommutable = Commutable; } // shifted register def rs : t2PseudoInst< (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), - Size4Bytes, IIC_iALUsi, + 4, IIC_iALUsi, [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>; } } @@ -1164,10 +1164,10 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), let neverHasSideEffects = 1, isReMaterializable = 1 in def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), - Size4Bytes, IIC_iALUi, []>; + 4, IIC_iALUi, []>; def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, nohash_imm:$id, pred:$p), - Size4Bytes, IIC_iALUi, + 4, IIC_iALUi, []>; @@ -2709,14 +2709,14 @@ defm t2TEQ : T2I_cmp_irs<0b0100, "teq", let neverHasSideEffects = 1 in { def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm, pred:$p), - Size4Bytes, IIC_iCMOVr, + 4, IIC_iCMOVr, [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $Rd">; let isMoveImm = 1 in def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm, pred:$p), - Size4Bytes, IIC_iCMOVi, + 4, IIC_iCMOVi, [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>, RegConstraint<"$false = $Rd">; @@ -2823,7 +2823,7 @@ def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "", let Inst{3-0} = 0b1111; } -class T2I_ldrex opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, +class T2I_ldrex opcod, dag oops, dag iops, AddrMode am, int sz, InstrItinClass itin, string opc, string asm, string cstr, list pattern, bits<4> rt2 = 0b1111> : Thumb2I { @@ -2839,7 +2839,7 @@ class T2I_ldrex opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, let Inst{19-16} = addr; let Inst{15-12} = Rt; } -class T2I_strex opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, +class T2I_strex opcod, dag oops, dag iops, AddrMode am, int sz, InstrItinClass itin, string opc, string asm, string cstr, list pattern, bits<4> rt2 = 0b1111> : Thumb2I { @@ -2859,13 +2859,13 @@ class T2I_strex opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, let mayLoad = 1 in { def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "ldrexb", "\t$Rt, $addr", "", []>; def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "ldrexh", "\t$Rt, $addr", "", []>; def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "ldrex", "\t$Rt, $addr", "", []> { let Inst{31-27} = 0b11101; let Inst{26-20} = 0b0000101; @@ -2880,7 +2880,7 @@ def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr), let hasExtraDefRegAllocReq = 1 in def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", "", [], {?, ?, ?, ?}> { bits<4> Rt2; @@ -2891,14 +2891,14 @@ def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), let mayStore = 1, Constraints = "@earlyclobber $Rd" in { def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "strexb", "\t$Rd, $Rt, $addr", "", []>; def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "strexh", "\t$Rd, $Rt, $addr", "", []>; def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "strex", "\t$Rd, $Rt, $addr", "", []> { let Inst{31-27} = 0b11101; @@ -2917,7 +2917,7 @@ def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr), - AddrModeNone, Size4Bytes, NoItinerary, + AddrModeNone, 4, NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], {?, ?, ?, ?}> { bits<4> Rt2; @@ -2955,7 +2955,7 @@ let Defs = QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), - AddrModeNone, SizeSpecial, NoItinerary, "", "", + AddrModeNone, 0, NoItinerary, "", "", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, Requires<[IsThumb2, HasVFP2]>; } @@ -2964,7 +2964,7 @@ let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), - AddrModeNone, SizeSpecial, NoItinerary, "", "", + AddrModeNone, 0, NoItinerary, "", "", [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, Requires<[IsThumb2, NoVFP]>; } @@ -2980,7 +2980,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), - Size4Bytes, IIC_iLoad_mBr, [], + 4, IIC_iLoad_mBr, [], (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, RegConstraint<"$Rn = $wb">; @@ -3004,17 +3004,17 @@ def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br, let isNotDuplicable = 1, isIndirectBranch = 1 in { def t2BR_JT : t2PseudoInst<(outs), (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, + 0, IIC_Br, [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; // FIXME: Add a non-pc based case that can be predicated. def t2TBB_JT : t2PseudoInst<(outs), (ins GPR:$index, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, []>; + 0, IIC_Br, []>; def t2TBH_JT : t2PseudoInst<(outs), (ins GPR:$index, i32imm:$jt, i32imm:$id), - SizeSpecial, IIC_Br, []>; + 0, IIC_Br, []>; def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br, "tbb", "\t[$Rn, $Rm]", []> { @@ -3069,7 +3069,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], Uses = [SP] in def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops), - Size4Bytes, IIC_Br, [], + 4, IIC_Br, [], (t2B uncondbrtarget:$dst)>, Requires<[IsThumb2, IsDarwin]>; } @@ -3077,7 +3077,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { // IT block let Defs = [ITSTATE] in def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), - AddrModeNone, Size2Bytes, IIC_iALUx, + AddrModeNone, 2, IIC_iALUx, "it$mask\t$cc", "", []> { // 16-bit instruction. let Inst{31-16} = 0x0000; diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index e839bab78a6..f1f3cb9c2ec 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -990,12 +990,12 @@ def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), let neverHasSideEffects = 1 in { def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p), - Size4Bytes, IIC_fpUNA64, + 4, IIC_fpUNA64, [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, RegConstraint<"$Dn = $Dd">; def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p), - Size4Bytes, IIC_fpUNA32, + 4, IIC_fpUNA32, [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, RegConstraint<"$Sn = $Sd">; } // neverHasSideEffects diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index df3a14f3a8e..aea1d1d145a 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -1296,13 +1296,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, uint64_t TSFlags = Desc.TSFlags; if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) return; + int Size; - // Basic size info comes from the TSFlags field. - switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { - default: llvm_unreachable("Unexpected instruction size!"); - case ARMII::Size2Bytes: Size = 2; break; - case ARMII::Size4Bytes: Size = 4; break; - } + if (Desc.getSize() == 2 || Desc.getSize() == 4) + Size = Desc.getSize(); + else + llvm_unreachable("Unexpected instruction size!"); + uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); // Thumb 32-bit wide instructions need to emit the high order halfword // first. diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 18d4db080a2..9c5f945d8c9 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -257,8 +257,10 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, OS << " { "; OS << Num << ",\t" << MinOperands << ",\t" - << Inst.Operands.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) - << ",\t\"" << Inst.TheDef->getName() << "\", 0"; + << Inst.Operands.NumDefs << ",\t" + << getItinClassNumber(Inst.TheDef) << ",\t" + << Inst.TheDef->getValueAsInt("Size") << ",\t\"" + << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... if (Inst.isReturn) OS << "|(1<