mirror of
https://github.com/RPCS3/llvm-mirror.git
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[AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 309062
This commit is contained in:
Eugene Zelenko
parent
60633f66f7
commit
c6903d856f
@ -1,4 +1,4 @@
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//===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
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//===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -19,30 +19,39 @@
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#include "AArch64Subtarget.h"
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#include "InstPrinter/AArch64InstPrinter.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCLinkerOptimizationHint.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <memory>
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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@ -57,7 +66,7 @@ class AArch64AsmPrinter : public AsmPrinter {
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public:
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AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
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SM(*this), AArch64FI(nullptr) {}
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SM(*this) {}
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StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
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@ -118,7 +127,8 @@ private:
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MCSymbol *GetCPISymbol(unsigned CPID) const override;
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void EmitEndOfAsmFile(Module &M) override;
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AArch64FunctionInfo *AArch64FI;
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AArch64FunctionInfo *AArch64FI = nullptr;
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/// \brief Emit the LOHs contained in AArch64FI.
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void EmitLOHs();
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@ -126,13 +136,12 @@ private:
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/// Emit instruction to set float register to zero.
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void EmitFMov0(const MachineInstr &MI);
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typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
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using MInstToMCSymbol = std::map<const MachineInstr *, MCSymbol *>;
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MInstToMCSymbol LOHInstToLabel;
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};
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} // end of anonymous namespace
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//===----------------------------------------------------------------------===//
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} // end anonymous namespace
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void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
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{
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@ -1,4 +1,4 @@
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//===--- AArch64CallLowering.h - Call lowering ------------------*- C++ -*-===//
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//===- AArch64CallLowering.h - Call lowering --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -17,12 +17,18 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/IR/CallingConv.h"
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#include <cstdint>
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#include <functional>
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namespace llvm {
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class AArch64TargetLowering;
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class CCValAssign;
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class DataLayout;
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class MachineIRBuilder;
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class MachineRegisterInfo;
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class Type;
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class AArch64CallLowering: public CallLowering {
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public:
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@ -39,14 +45,13 @@ public:
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ArrayRef<ArgInfo> OrigArgs) const override;
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private:
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typedef std::function<void(MachineIRBuilder &, Type *, unsigned,
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CCValAssign &)>
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RegHandler;
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using RegHandler = std::function<void(MachineIRBuilder &, Type *, unsigned,
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CCValAssign &)>;
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typedef std::function<void(MachineIRBuilder &, int, CCValAssign &)>
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MemHandler;
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using MemHandler =
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std::function<void(MachineIRBuilder &, int, CCValAssign &)>;
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typedef std::function<void(unsigned, uint64_t)> SplitArgTy;
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using SplitArgTy = std::function<void(unsigned, uint64_t)>;
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void splitToValueTypes(const ArgInfo &OrigArgInfo,
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SmallVectorImpl<ArgInfo> &SplitArgs,
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@ -60,20 +60,26 @@
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#include "AArch64.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <cassert>
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#include <cstdlib>
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#include <tuple>
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@ -84,6 +90,7 @@ using namespace llvm;
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STATISTIC(NumConditionsAdjusted, "Number of conditions adjusted");
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namespace {
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class AArch64ConditionOptimizer : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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MachineDominatorTree *DomTree;
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@ -92,12 +99,14 @@ class AArch64ConditionOptimizer : public MachineFunctionPass {
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public:
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// Stores immediate, compare instruction opcode and branch condition (in this
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// order) of adjusted comparison.
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typedef std::tuple<int, unsigned, AArch64CC::CondCode> CmpInfo;
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using CmpInfo = std::tuple<int, unsigned, AArch64CC::CondCode>;
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static char ID;
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AArch64ConditionOptimizer() : MachineFunctionPass(ID) {
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initializeAArch64ConditionOptimizerPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);
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CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
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@ -105,10 +114,12 @@ public:
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bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
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int ToImm);
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "AArch64 Condition Optimizer";
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}
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};
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} // end anonymous namespace
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char AArch64ConditionOptimizer::ID = 0;
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@ -1,4 +1,4 @@
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//==-- AArch64ExpandPseudoInsts.cpp - Expand pseudo instructions --*- C++ -*-=//
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//===- AArch64ExpandPseudoInsts.cpp - Expand pseudo instructions ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -18,24 +18,44 @@
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#include "AArch64Subtarget.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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#include <limits>
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#include <utility>
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using namespace llvm;
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#define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
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namespace {
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class AArch64ExpandPseudo : public MachineFunctionPass {
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public:
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const AArch64InstrInfo *TII;
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static char ID;
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AArch64ExpandPseudo() : MachineFunctionPass(ID) {
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initializeAArch64ExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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const AArch64InstrInfo *TII;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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StringRef getPassName() const override { return AARCH64_EXPAND_PSEUDO_NAME; }
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@ -55,8 +75,10 @@ private:
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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};
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} // end anonymous namespace
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char AArch64ExpandPseudo::ID = 0;
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}
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INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
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AARCH64_EXPAND_PSEUDO_NAME, false, false)
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@ -151,12 +173,12 @@ static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
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/// This allows us to materialize constants like |A|B|A|A| or |A|B|C|A| (order
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/// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
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/// an ORR instruction.
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///
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static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const AArch64InstrInfo *TII) {
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typedef DenseMap<uint64_t, unsigned> CountMap;
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using CountMap = DenseMap<uint64_t, unsigned>;
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CountMap Counts;
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// Scan the constant and count how often every chunk occurs.
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@ -242,7 +264,7 @@ static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
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/// starts a contiguous sequence of ones if we look at the bits from the LSB
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/// towards the MSB.
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static bool isStartChunk(uint64_t Chunk) {
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if (Chunk == 0 || Chunk == UINT64_MAX)
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if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
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return false;
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return isMask_64(~Chunk);
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@ -252,7 +274,7 @@ static bool isStartChunk(uint64_t Chunk) {
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/// ends a contiguous sequence of ones if we look at the bits from the LSB
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/// towards the MSB.
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static bool isEndChunk(uint64_t Chunk) {
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if (Chunk == 0 || Chunk == UINT64_MAX)
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if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
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return false;
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return isMask_64(Chunk);
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@ -285,7 +307,6 @@ static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
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///
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/// We are also looking for constants like |S|A|B|E| where the contiguous
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/// sequence of ones wraps around the MSB into the LSB.
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///
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static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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@ -668,7 +689,6 @@ bool AArch64ExpandPseudo::expandCMP_SWAP(
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bool AArch64ExpandPseudo::expandCMP_SWAP_128(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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MachineOperand &DestLo = MI.getOperand(0);
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@ -1,4 +1,4 @@
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//===-- AArch64FalkorHWPFFix.cpp - Avoid HW prefetcher pitfalls on Falkor--===//
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//===- AArch64FalkorHWPFFix.cpp - Avoid HW prefetcher pitfalls on Falkor --===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -15,21 +15,41 @@
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/None.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/ScalarEvolution.h"
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#include "llvm/Analysis/ScalarEvolutionExpressions.h"
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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#include <iterator>
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#include <utility>
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using namespace llvm;
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@ -60,6 +80,7 @@ private:
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class FalkorMarkStridedAccessesLegacy : public FunctionPass {
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public:
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static char ID; // Pass ID, replacement for typeid
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FalkorMarkStridedAccessesLegacy() : FunctionPass(ID) {
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initializeFalkorMarkStridedAccessesLegacyPass(
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*PassRegistry::getPassRegistry());
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@ -78,9 +99,11 @@ public:
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bool runOnFunction(Function &F) override;
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};
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} // namespace
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} // end anonymous namespace
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char FalkorMarkStridedAccessesLegacy::ID = 0;
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INITIALIZE_PASS_BEGIN(FalkorMarkStridedAccessesLegacy, DEBUG_TYPE,
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"Falkor HW Prefetch Fix", false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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@ -165,7 +188,7 @@ public:
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bool runOnMachineFunction(MachineFunction &Fn) override;
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virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@ -186,17 +209,16 @@ private:
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/// Bits from load opcodes used to compute HW prefetcher instruction tags.
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struct LoadInfo {
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LoadInfo()
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: DestReg(0), BaseReg(0), BaseRegIdx(-1), OffsetOpnd(nullptr),
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IsPrePost(false) {}
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unsigned DestReg;
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unsigned BaseReg;
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int BaseRegIdx;
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const MachineOperand *OffsetOpnd;
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bool IsPrePost;
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LoadInfo() = default;
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unsigned DestReg = 0;
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unsigned BaseReg = 0;
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int BaseRegIdx = -1;
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const MachineOperand *OffsetOpnd = nullptr;
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bool IsPrePost = false;
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};
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} // namespace
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} // end anonymous namespace
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char FalkorHWPFFix::ID = 0;
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@ -1,4 +1,4 @@
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//===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
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//===- AArch6464FastISel.cpp - AArch64 FastISel implementation ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
|
||||
@ -53,6 +53,7 @@
|
||||
#include "llvm/IR/Instruction.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/IR/IntrinsicInst.h"
|
||||
#include "llvm/IR/Intrinsics.h"
|
||||
#include "llvm/IR/Operator.h"
|
||||
#include "llvm/IR/Type.h"
|
||||
#include "llvm/IR/User.h"
|
||||
@ -63,6 +64,7 @@
|
||||
#include "llvm/Support/AtomicOrdering.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/CodeGen.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include <algorithm>
|
||||
@ -78,10 +80,10 @@ namespace {
|
||||
class AArch64FastISel final : public FastISel {
|
||||
class Address {
|
||||
public:
|
||||
typedef enum {
|
||||
using BaseKind = enum {
|
||||
RegBase,
|
||||
FrameIndexBase
|
||||
} BaseKind;
|
||||
};
|
||||
|
||||
private:
|
||||
BaseKind Kind = RegBase;
|
||||
@ -944,7 +946,6 @@ bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
|
||||
EVT evt = TLI.getValueType(DL, Ty, true);
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
|
||||
//===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -20,6 +20,7 @@
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/ADT/StringRef.h"
|
||||
#include "llvm/ADT/iterator_range.h"
|
||||
#include "llvm/Analysis/AliasAnalysis.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
@ -64,7 +65,7 @@ static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
|
||||
|
||||
namespace {
|
||||
|
||||
typedef struct LdStPairFlags {
|
||||
using LdStPairFlags = struct LdStPairFlags {
|
||||
// If a matching instruction is found, MergeForward is set to true if the
|
||||
// merge is to remove the first instruction and replace the second with
|
||||
// a pair-wise insn, and false if the reverse is true.
|
||||
@ -83,8 +84,7 @@ typedef struct LdStPairFlags {
|
||||
|
||||
void setSExtIdx(int V) { SExtIdx = V; }
|
||||
int getSExtIdx() const { return SExtIdx; }
|
||||
|
||||
} LdStPairFlags;
|
||||
};
|
||||
|
||||
struct AArch64LoadStoreOpt : public MachineFunctionPass {
|
||||
static char ID;
|
||||
@ -101,7 +101,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
|
||||
// Track which registers have been modified and used.
|
||||
BitVector ModifiedRegs, UsedRegs;
|
||||
|
||||
virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.addRequired<AAResultsWrapperPass>();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
|
||||
@ -23,6 +23,8 @@
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class MachineInstr;
|
||||
|
||||
/// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and
|
||||
/// contains private AArch64-specific information for each MachineFunction.
|
||||
class AArch64FunctionInfo final : public MachineFunctionInfo {
|
||||
@ -145,7 +147,7 @@ public:
|
||||
unsigned getVarArgsFPRSize() const { return VarArgsFPRSize; }
|
||||
void setVarArgsFPRSize(unsigned Size) { VarArgsFPRSize = Size; }
|
||||
|
||||
typedef SmallPtrSet<const MachineInstr *, 16> SetOfInstructions;
|
||||
using SetOfInstructions = SmallPtrSet<const MachineInstr *, 16>;
|
||||
|
||||
const SetOfInstructions &getLOHRelated() const { return LOHRelated; }
|
||||
|
||||
@ -157,7 +159,7 @@ public:
|
||||
SmallVector<const MachineInstr *, 3> Args;
|
||||
|
||||
public:
|
||||
typedef ArrayRef<const MachineInstr *> LOHArgs;
|
||||
using LOHArgs = ArrayRef<const MachineInstr *>;
|
||||
|
||||
MILOHDirective(MCLOHType Kind, LOHArgs Args)
|
||||
: Kind(Kind), Args(Args.begin(), Args.end()) {
|
||||
@ -168,8 +170,8 @@ public:
|
||||
LOHArgs getArgs() const { return Args; }
|
||||
};
|
||||
|
||||
typedef MILOHDirective::LOHArgs MILOHArgs;
|
||||
typedef SmallVector<MILOHDirective, 32> MILOHContainer;
|
||||
using MILOHArgs = MILOHDirective::LOHArgs;
|
||||
using MILOHContainer = SmallVector<MILOHDirective, 32>;
|
||||
|
||||
const MILOHContainer &getLOHContainer() const { return LOHContainerSet; }
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//=- AArch64PromoteConstant.cpp --- Promote constant to global for AArch64 -==//
|
||||
//==- AArch64PromoteConstant.cpp - Promote constant to global for AArch64 --==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -22,23 +22,31 @@
|
||||
|
||||
#include "AArch64.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/IR/BasicBlock.h"
|
||||
#include "llvm/IR/Constant.h"
|
||||
#include "llvm/IR/Constants.h"
|
||||
#include "llvm/IR/Dominators.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/GlobalValue.h"
|
||||
#include "llvm/IR/GlobalVariable.h"
|
||||
#include "llvm/IR/IRBuilder.h"
|
||||
#include "llvm/IR/InlineAsm.h"
|
||||
#include "llvm/IR/InstIterator.h"
|
||||
#include "llvm/IR/Instruction.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/IR/IntrinsicInst.h"
|
||||
#include "llvm/IR/Module.h"
|
||||
#include "llvm/IR/Type.h"
|
||||
#include "llvm/Pass.h"
|
||||
#include "llvm/Support/Casting.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <utility>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -56,6 +64,7 @@ STATISTIC(NumPromotedUses, "Number of promoted constants uses");
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
namespace {
|
||||
|
||||
/// Promotes interesting constant into global variables.
|
||||
/// The motivating example is:
|
||||
/// static const uint16_t TableA[32] = {
|
||||
@ -83,13 +92,12 @@ namespace {
|
||||
/// Therefore the final assembly final has 4 different loads. With this pass
|
||||
/// enabled, only one load is issued for the constants.
|
||||
class AArch64PromoteConstant : public ModulePass {
|
||||
|
||||
public:
|
||||
struct PromotedConstant {
|
||||
bool ShouldConvert = false;
|
||||
GlobalVariable *GV = nullptr;
|
||||
};
|
||||
typedef SmallDenseMap<Constant *, PromotedConstant, 16> PromotionCacheTy;
|
||||
using PromotionCacheTy = SmallDenseMap<Constant *, PromotedConstant, 16>;
|
||||
|
||||
struct UpdateRecord {
|
||||
Constant *C;
|
||||
@ -101,6 +109,7 @@ public:
|
||||
};
|
||||
|
||||
static char ID;
|
||||
|
||||
AArch64PromoteConstant() : ModulePass(ID) {
|
||||
initializeAArch64PromoteConstantPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
@ -135,9 +144,9 @@ private:
|
||||
}
|
||||
|
||||
/// Type to store a list of Uses.
|
||||
typedef SmallVector<std::pair<Instruction *, unsigned>, 4> Uses;
|
||||
using Uses = SmallVector<std::pair<Instruction *, unsigned>, 4>;
|
||||
/// Map an insertion point to all the uses it dominates.
|
||||
typedef DenseMap<Instruction *, Uses> InsertionPoints;
|
||||
using InsertionPoints = DenseMap<Instruction *, Uses>;
|
||||
|
||||
/// Find the closest point that dominates the given Use.
|
||||
Instruction *findInsertionPoint(Instruction &User, unsigned OpNo);
|
||||
@ -212,6 +221,7 @@ private:
|
||||
InsertPts.erase(OldInstr);
|
||||
}
|
||||
};
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
char AArch64PromoteConstant::ID = 0;
|
||||
@ -357,7 +367,6 @@ Instruction *AArch64PromoteConstant::findInsertionPoint(Instruction &User,
|
||||
bool AArch64PromoteConstant::isDominated(Instruction *NewPt, Instruction *User,
|
||||
unsigned OpNo,
|
||||
InsertionPoints &InsertPts) {
|
||||
|
||||
DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>(
|
||||
*NewPt->getParent()->getParent()).getDomTree();
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- AArch64TargetTransformInfo.h - AArch64 specific TTI -----*- C++ -*-===//
|
||||
//===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -18,17 +18,31 @@
|
||||
#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
|
||||
|
||||
#include "AArch64.h"
|
||||
#include "AArch64Subtarget.h"
|
||||
#include "AArch64TargetMachine.h"
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/Analysis/TargetTransformInfo.h"
|
||||
#include "llvm/CodeGen/BasicTTIImpl.h"
|
||||
#include "llvm/Target/TargetLowering.h"
|
||||
#include <algorithm>
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/Intrinsics.h"
|
||||
#include <cstdint>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class APInt;
|
||||
class Instruction;
|
||||
class IntrinsicInst;
|
||||
class Loop;
|
||||
class SCEV;
|
||||
class ScalarEvolution;
|
||||
class Type;
|
||||
class Value;
|
||||
class VectorType;
|
||||
|
||||
class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
|
||||
typedef BasicTTIImplBase<AArch64TTIImpl> BaseT;
|
||||
typedef TargetTransformInfo TTI;
|
||||
using BaseT = BasicTTIImplBase<AArch64TTIImpl>;
|
||||
using TTI = TargetTransformInfo;
|
||||
|
||||
friend BaseT;
|
||||
|
||||
const AArch64Subtarget *ST;
|
||||
@ -157,4 +171,4 @@ public:
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
#endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
|
||||
//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
@ -14,160 +14,162 @@
|
||||
#include "AArch64ExternalSymbolizer.h"
|
||||
#include "AArch64Subtarget.h"
|
||||
#include "MCTargetDesc/AArch64AddressingModes.h"
|
||||
#include "MCTargetDesc/AArch64MCTargetDesc.h"
|
||||
#include "Utils/AArch64BaseInfo.h"
|
||||
#include "llvm-c/Disassembler.h"
|
||||
#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
|
||||
#include "llvm/MC/MCFixedLenDisassembler.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/Support/Compiler.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
#include <algorithm>
|
||||
#include <memory>
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "aarch64-disassembler"
|
||||
|
||||
// Pull DecodeStatus and its enum values into the global namespace.
|
||||
typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
|
||||
using DecodeStatus = MCDisassembler::DecodeStatus;
|
||||
|
||||
// Forward declare these because the autogenerated code will reference them.
|
||||
// Definitions are further down.
|
||||
static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
|
||||
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
|
||||
unsigned RegNo, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
|
||||
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
|
||||
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
|
||||
unsigned RegNo, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
|
||||
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
|
||||
unsigned RegNo, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
|
||||
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn,
|
||||
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn,
|
||||
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn,
|
||||
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn,
|
||||
static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
|
||||
unsigned RegNo,
|
||||
@ -196,9 +198,9 @@ static bool Check(DecodeStatus &Out, DecodeStatus In) {
|
||||
#include "AArch64GenDisassemblerTables.inc"
|
||||
#include "AArch64GenInstrInfo.inc"
|
||||
|
||||
#define Success llvm::MCDisassembler::Success
|
||||
#define Fail llvm::MCDisassembler::Fail
|
||||
#define SoftFail llvm::MCDisassembler::SoftFail
|
||||
#define Success MCDisassembler::Success
|
||||
#define Fail MCDisassembler::Fail
|
||||
#define SoftFail MCDisassembler::SoftFail
|
||||
|
||||
static MCDisassembler *createAArch64Disassembler(const Target &T,
|
||||
const MCSubtargetInfo &STI,
|
||||
@ -232,7 +234,7 @@ createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
|
||||
LLVMSymbolLookupCallback SymbolLookUp,
|
||||
void *DisInfo, MCContext *Ctx,
|
||||
std::unique_ptr<MCRelocationInfo> &&RelInfo) {
|
||||
return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo,
|
||||
return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
|
||||
SymbolLookUp, DisInfo);
|
||||
}
|
||||
|
||||
@ -587,7 +589,7 @@ static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
// scale{5} is asserted as 1 in tblgen.
|
||||
@ -596,14 +598,14 @@ static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
Inst.addOperand(MCOperand::createImm(64 - Imm));
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
int64_t ImmVal = Imm;
|
||||
const AArch64Disassembler *Dis =
|
||||
@ -619,14 +621,14 @@ static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address, const void *Decoder) {
|
||||
Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
|
||||
Inst.addOperand(MCOperand::createImm(Imm & 1));
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
const void *Decoder) {
|
||||
Inst.addOperand(MCOperand::createImm(Imm));
|
||||
@ -636,7 +638,7 @@ static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
const void *Decoder) {
|
||||
Inst.addOperand(MCOperand::createImm(Imm));
|
||||
@ -644,7 +646,7 @@ static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
|
||||
static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder) {
|
||||
// This decoder exists to add the dummy Lane operand to the MCInst, which must
|
||||
@ -667,78 +669,78 @@ static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
|
||||
unsigned Add) {
|
||||
Inst.addOperand(MCOperand::createImm(Add - Imm));
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
|
||||
unsigned Add) {
|
||||
Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftRImm(Inst, Imm, 64);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftRImm(Inst, Imm, 32);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftRImm(Inst, Imm, 16);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftRImm(Inst, Imm, 8);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftLImm(Inst, Imm, 64);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftLImm(Inst, Imm, 32);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftLImm(Inst, Imm, 16);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
|
||||
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
return DecodeVecShiftLImm(Inst, Imm, 8);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
@ -799,7 +801,7 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
@ -832,8 +834,8 @@ static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rt = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
@ -893,8 +895,8 @@ static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rt = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
@ -1078,8 +1080,8 @@ static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rt = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
@ -1161,7 +1163,7 @@ static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rt = fieldFromInstruction(insn, 0, 5);
|
||||
@ -1290,8 +1292,8 @@ static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
@ -1347,8 +1349,8 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
@ -1378,7 +1380,7 @@ static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
@ -1417,8 +1419,8 @@ static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned cmode = fieldFromInstruction(insn, 12, 4);
|
||||
@ -1435,7 +1437,7 @@ static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
|
||||
@ -1454,7 +1456,7 @@ static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
@ -1490,7 +1492,7 @@ static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
int64_t imm = fieldFromInstruction(insn, 0, 26);
|
||||
@ -1507,8 +1509,8 @@ static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
uint64_t op1 = fieldFromInstruction(insn, 16, 3);
|
||||
uint64_t op2 = fieldFromInstruction(insn, 5, 3);
|
||||
@ -1531,7 +1533,7 @@ static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
|
||||
return Fail;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
|
||||
static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr, const void *Decoder) {
|
||||
uint64_t Rt = fieldFromInstruction(insn, 0, 5);
|
||||
uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user