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[AArch64][SVE] Remove index_vector node.
Since index_vector is lowered into step_vector in D100816, we can just remove index_vector, use step_vector for codegen directly. Differential Revision: https://reviews.llvm.org/D101593
This commit is contained in:
Jun Ma
parent
cd06af4e32
commit
c6d9235341
@ -15360,19 +15360,6 @@ static SDValue performGlobalAddressCombine(SDNode *N, SelectionDAG &DAG,
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DAG.getConstant(MinOffset, DL, MVT::i64));
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}
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static SDValue performStepVectorCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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SelectionDAG &DAG) {
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if (!DCI.isAfterLegalizeDAG())
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return SDValue();
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SDLoc DL(N);
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EVT VT = N->getValueType(0);
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SDValue StepVal = N->getOperand(0);
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SDValue Zero = DAG.getConstant(0, DL, StepVal.getValueType());
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return DAG.getNode(AArch64ISD::INDEX_VECTOR, DL, VT, Zero, StepVal);
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}
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// Turns the vector of indices into a vector of byte offstes by scaling Offset
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// by (BitWidth / 8).
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static SDValue getScaledOffsetForBitWidth(SelectionDAG &DAG, SDValue Offset,
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@ -15956,8 +15943,6 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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return performExtractVectorEltCombine(N, DAG);
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case ISD::VECREDUCE_ADD:
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return performVecReduceAddCombine(N, DCI.DAG, Subtarget);
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case ISD::STEP_VECTOR:
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return performStepVectorCombine(N, DCI, DAG);
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN:
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switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
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@ -259,10 +259,8 @@ def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
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def SDT_AArch64DUP_PRED : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 3>, SDTCisVec<1>, SDTCVecEltisVT<1,i1>]>;
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def AArch64dup_mt : SDNode<"AArch64ISD::DUP_MERGE_PASSTHRU", SDT_AArch64DUP_PRED>;
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def SDT_IndexVector : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<2>]>;
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def index_vector : SDNode<"AArch64ISD::INDEX_VECTOR", SDT_IndexVector, []>;
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def index_vector_oneuse : PatFrag<(ops node:$base, node:$idx),
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(index_vector node:$base, node:$idx), [{
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def step_vector_oneuse : PatFrag<(ops node:$idx),
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(step_vector node:$idx), [{
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return N->hasOneUse();
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}]>;
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@ -1370,10 +1368,10 @@ let Predicates = [HasSVE] in {
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defm INCP_ZP : sve_int_count_v<0b10000, "incp">;
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defm DECP_ZP : sve_int_count_v<0b10100, "decp">;
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defm INDEX_RR : sve_int_index_rr<"index", index_vector, index_vector_oneuse, AArch64mul_p_oneuse>;
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defm INDEX_IR : sve_int_index_ir<"index", index_vector, index_vector_oneuse, AArch64mul_p, AArch64mul_p_oneuse>;
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defm INDEX_RI : sve_int_index_ri<"index", index_vector, index_vector_oneuse>;
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defm INDEX_II : sve_int_index_ii<"index", index_vector, index_vector_oneuse>;
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defm INDEX_RR : sve_int_index_rr<"index", step_vector, step_vector_oneuse, AArch64mul_p_oneuse>;
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defm INDEX_IR : sve_int_index_ir<"index", step_vector, step_vector_oneuse, AArch64mul_p, AArch64mul_p_oneuse>;
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defm INDEX_RI : sve_int_index_ri<"index", step_vector, step_vector_oneuse>;
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defm INDEX_II : sve_int_index_ii<"index", step_vector, step_vector_oneuse>;
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// Unpredicated shifts
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defm ASR_ZZI : sve_int_bin_cons_shift_imm_right<0b00, "asr", AArch64asr_p>;
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@ -4800,23 +4800,23 @@ multiclass sve_int_index_ii<string asm, SDPatternOperator op, SDPatternOperator
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def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
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def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
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def : Pat<(nxv16i8 (op simm5_8b:$imm5, simm5_8b:$imm5b)),
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(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, simm5_8b:$imm5b)>;
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def : Pat<(nxv8i16 (op simm5_16b:$imm5, simm5_16b:$imm5b)),
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(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, simm5_16b:$imm5b)>;
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def : Pat<(nxv4i32 (op simm5_32b:$imm5, simm5_32b:$imm5b)),
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(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, simm5_32b:$imm5b)>;
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def : Pat<(nxv2i64 (op simm5_64b:$imm5, simm5_64b:$imm5b)),
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(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, simm5_64b:$imm5b)>;
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def : Pat<(nxv16i8 (op simm5_8b:$imm5b)),
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(!cast<Instruction>(NAME # "_B") (i32 0), simm5_8b:$imm5b)>;
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def : Pat<(nxv8i16 (op simm5_16b:$imm5b)),
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(!cast<Instruction>(NAME # "_H") (i32 0), simm5_16b:$imm5b)>;
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def : Pat<(nxv4i32 (op simm5_32b:$imm5b)),
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(!cast<Instruction>(NAME # "_S") (i32 0), simm5_32b:$imm5b)>;
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def : Pat<(nxv2i64 (op simm5_64b:$imm5b)),
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(!cast<Instruction>(NAME # "_D") (i64 0), simm5_64b:$imm5b)>;
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// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
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def : Pat<(add (nxv16i8 (oneuseop (i32 0), simm5_8b:$imm5b)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
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// add(step_vector(step), dup(X)) -> index(X, step).
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def : Pat<(add (nxv16i8 (oneuseop simm5_8b:$imm5b)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
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(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, simm5_8b:$imm5b)>;
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def : Pat<(add (nxv8i16 (oneuseop (i32 0), simm5_16b:$imm5b)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
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def : Pat<(add (nxv8i16 (oneuseop simm5_16b:$imm5b)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
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(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, simm5_16b:$imm5b)>;
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def : Pat<(add (nxv4i32 (oneuseop (i32 0), simm5_32b:$imm5b)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
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def : Pat<(add (nxv4i32 (oneuseop simm5_32b:$imm5b)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
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(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, simm5_32b:$imm5b)>;
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def : Pat<(add (nxv2i64 (oneuseop (i64 0), simm5_64b:$imm5b)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
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def : Pat<(add (nxv2i64 (oneuseop simm5_64b:$imm5b)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
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(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, simm5_64b:$imm5b)>;
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}
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@ -4843,43 +4843,43 @@ multiclass sve_int_index_ir<string asm, SDPatternOperator op, SDPatternOperator
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def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
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def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
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def : Pat<(nxv16i8 (op simm5_8b:$imm5, GPR32:$Rm)),
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(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
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def : Pat<(nxv8i16 (op simm5_16b:$imm5, GPR32:$Rm)),
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(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
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def : Pat<(nxv4i32 (op simm5_32b:$imm5, GPR32:$Rm)),
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(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
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def : Pat<(nxv2i64 (op simm5_64b:$imm5, GPR64:$Rm)),
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(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
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// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
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def : Pat<(add (nxv16i8 (oneuseop (i32 0), GPR32:$Rm)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
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(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (nxv8i16 (oneuseop (i32 0), GPR32:$Rm)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
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(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (nxv4i32 (oneuseop (i32 0), GPR32:$Rm)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
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(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (nxv2i64 (oneuseop (i64 0), GPR64:$Rm)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
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(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
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// mul(index_vector(0, 1), dup(Y)) -> index_vector(0, Y).
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def : Pat<(mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 0), (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
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def : Pat<(nxv16i8 (op GPR32:$Rm)),
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(!cast<Instruction>(NAME # "_B") (i32 0), GPR32:$Rm)>;
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def : Pat<(mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 0), (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
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def : Pat<(nxv8i16 (op GPR32:$Rm)),
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(!cast<Instruction>(NAME # "_H") (i32 0), GPR32:$Rm)>;
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def : Pat<(mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 0), (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
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def : Pat<(nxv4i32 (op GPR32:$Rm)),
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(!cast<Instruction>(NAME # "_S") (i32 0), GPR32:$Rm)>;
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def : Pat<(mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 0), (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
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def : Pat<(nxv2i64 (op GPR64:$Rm)),
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(!cast<Instruction>(NAME # "_D") (i64 0), GPR64:$Rm)>;
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// add(mul(index_vector(0, 1), dup(Y), dup(X)) -> index_vector(X, Y).
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def : Pat<(add (muloneuseop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 0), (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
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// add(step_vector(step), dup(X)) -> index(X, step).
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def : Pat<(add (nxv16i8 (oneuseop GPR32:$Rm)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
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(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (muloneuseop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 0), (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
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def : Pat<(add (nxv8i16 (oneuseop GPR32:$Rm)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
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(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (muloneuseop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 0), (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
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def : Pat<(add (nxv4i32 (oneuseop GPR32:$Rm)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
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(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (muloneuseop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 0), (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
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def : Pat<(add (nxv2i64 (oneuseop GPR64:$Rm)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
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(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
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// mul(step_vector(1), dup(Y)) -> index(0, Y).
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def : Pat<(mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_B") (i32 0), GPR32:$Rm)>;
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def : Pat<(mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_H") (i32 0), GPR32:$Rm)>;
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def : Pat<(mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_S") (i32 0), GPR32:$Rm)>;
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def : Pat<(mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
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(!cast<Instruction>(NAME # "_D") (i64 0), GPR64:$Rm)>;
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// add(mul(step_vector(1), dup(Y), dup(X)) -> index(X, Y).
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def : Pat<(add (muloneuseop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
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(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (muloneuseop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
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(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (muloneuseop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
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(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
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def : Pat<(add (muloneuseop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
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(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
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}
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@ -4906,23 +4906,14 @@ multiclass sve_int_index_ri<string asm, SDPatternOperator op, SDPatternOperator
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def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
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def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
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def : Pat<(nxv16i8 (op GPR32:$Rm, simm5_8b:$imm5)),
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// add(step_vector(step), dup(X)) -> index(X, step).
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def : Pat<(add (nxv16i8 (oneuseop simm5_8b:$imm5)), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_B") GPR32:$Rm, simm5_8b:$imm5)>;
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def : Pat<(nxv8i16 (op GPR32:$Rm, simm5_16b:$imm5)),
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def : Pat<(add (nxv8i16 (oneuseop simm5_16b:$imm5)), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_H") GPR32:$Rm, simm5_16b:$imm5)>;
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def : Pat<(nxv4i32 (op GPR32:$Rm, simm5_32b:$imm5)),
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def : Pat<(add (nxv4i32 (oneuseop simm5_32b:$imm5)), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_S") GPR32:$Rm, simm5_32b:$imm5)>;
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def : Pat<(nxv2i64 (op GPR64:$Rm, simm5_64b:$imm5)),
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(!cast<Instruction>(NAME # "_D") GPR64:$Rm, simm5_64b:$imm5)>;
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// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
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def : Pat<(add (nxv16i8 (oneuseop (i32 0), simm5_8b:$imm5)), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_B") GPR32:$Rm, simm5_8b:$imm5)>;
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def : Pat<(add (nxv8i16 (oneuseop (i32 0), simm5_16b:$imm5)), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_H") GPR32:$Rm, simm5_16b:$imm5)>;
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def : Pat<(add (nxv4i32 (oneuseop (i32 0), simm5_32b:$imm5)), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "_S") GPR32:$Rm, simm5_32b:$imm5)>;
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def : Pat<(add (nxv2i64 (oneuseop (i64 0), simm5_64b:$imm5)), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
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def : Pat<(add (nxv2i64 (oneuseop simm5_64b:$imm5)), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
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(!cast<Instruction>(NAME # "_D") GPR64:$Rm, simm5_64b:$imm5)>;
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}
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@ -4949,29 +4940,24 @@ multiclass sve_int_index_rr<string asm, SDPatternOperator op, SDPatternOperator
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def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
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def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
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def : SVE_2_Op_Pat<nxv16i8, op, i32, i32, !cast<Instruction>(NAME # _B)>;
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def : SVE_2_Op_Pat<nxv8i16, op, i32, i32, !cast<Instruction>(NAME # _H)>;
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def : SVE_2_Op_Pat<nxv4i32, op, i32, i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_2_Op_Pat<nxv2i64, op, i64, i64, !cast<Instruction>(NAME # _D)>;
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// add(index_vector(zero, step), dup(X)) -> index_vector(X, step).
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def : Pat<(add (nxv16i8 (oneuseop (i32 0), GPR32:$Rm)), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
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// add(step_vector(step), dup(X)) -> index(X, step).
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def : Pat<(add (nxv16i8 (oneuseop GPR32:$Rm)), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
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(!cast<Instruction>(NAME # "_B") GPR32:$Rn, GPR32:$Rm)>;
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def : Pat<(add (nxv8i16 (oneuseop (i32 0), GPR32:$Rm)), (nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
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def : Pat<(add (nxv8i16 (oneuseop GPR32:$Rm)), (nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
|
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(!cast<Instruction>(NAME # "_H") GPR32:$Rn, GPR32:$Rm)>;
|
||||
def : Pat<(add (nxv4i32 (oneuseop (i32 0), GPR32:$Rm)), (nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
def : Pat<(add (nxv4i32 (oneuseop GPR32:$Rm)), (nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
(!cast<Instruction>(NAME # "_S") GPR32:$Rn, GPR32:$Rm)>;
|
||||
def : Pat<(add (nxv2i64 (oneuseop (i64 0), GPR64:$Rm)), (nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
|
||||
def : Pat<(add (nxv2i64 (oneuseop GPR64:$Rm)), (nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
|
||||
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, GPR64:$Rm)>;
|
||||
|
||||
// add(mul(index_vector(0, 1), dup(Y), dup(X)) -> index_vector(X, Y).
|
||||
def : Pat<(add (mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 0), (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
// add(mul(step_vector(1), dup(Y), dup(X)) -> index(X, Y).
|
||||
def : Pat<(add (mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
(!cast<Instruction>(NAME # "_B") GPR32:$Rn, GPR32:$Rm)>;
|
||||
def : Pat<(add (mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 0), (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),(nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
def : Pat<(add (mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),(nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
(!cast<Instruction>(NAME # "_H") GPR32:$Rn, GPR32:$Rm)>;
|
||||
def : Pat<(add (mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 0), (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),(nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
def : Pat<(add (mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),(nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
|
||||
(!cast<Instruction>(NAME # "_S") GPR32:$Rn, GPR32:$Rm)>;
|
||||
def : Pat<(add (mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 0), (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),(nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
|
||||
def : Pat<(add (mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),(nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
|
||||
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, GPR64:$Rm)>;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user