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https://github.com/RPCS3/llvm-mirror.git
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[Hexagon] Handle loads and stores of scalar predicate vectors
Handle v2i1, v4i1, and v8i1.
This commit is contained in:
Krzysztof Parzyszek
parent
d6942d76f2
commit
c6f27be4ce
@ -1726,6 +1726,12 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::STORE, VT, Custom);
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}
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// Custom-lower load/stores of boolean vectors.
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for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
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setOperationAction(ISD::LOAD, VT, Custom);
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setOperationAction(ISD::STORE, VT, Custom);
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}
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for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
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MVT::v2i32}) {
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setCondCodeAction(ISD::SETNE, VT, Expand);
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@ -2878,27 +2884,62 @@ HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
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SDValue
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HexagonTargetLowering::LowerLoad(SDValue Op, SelectionDAG &DAG) const {
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MVT Ty = ty(Op);
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const SDLoc &dl(Op);
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// Lower loads of scalar predicate vectors (v2i1, v4i1, v8i1) to loads of i1
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// followed by a TYPECAST.
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LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
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bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1);
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if (DoCast) {
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SDValue NL = DAG.getLoad(
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LN->getAddressingMode(), LN->getExtensionType(), MVT::i1, dl,
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LN->getChain(), LN->getBasePtr(), LN->getOffset(), LN->getPointerInfo(),
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/*MemoryVT*/ MVT::i1, LN->getAlign(), LN->getMemOperand()->getFlags(),
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LN->getAAInfo(), LN->getRanges());
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LN = cast<LoadSDNode>(NL.getNode());
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}
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unsigned ClaimAlign = LN->getAlignment();
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validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign);
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validateConstPtrAlignment(LN->getBasePtr(), dl, ClaimAlign);
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// Call LowerUnalignedLoad for all loads, it recognizes loads that
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// don't need extra aligning.
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return LowerUnalignedLoad(Op, DAG);
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SDValue LU = LowerUnalignedLoad(SDValue(LN, 0), DAG);
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if (DoCast) {
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SDValue TC = DAG.getNode(HexagonISD::TYPECAST, dl, Ty, LU);
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SDValue Ch = cast<LoadSDNode>(LU.getNode())->getChain();
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return DAG.getMergeValues({TC, Ch}, dl);
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}
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return LU;
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}
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SDValue
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HexagonTargetLowering::LowerStore(SDValue Op, SelectionDAG &DAG) const {
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const SDLoc &dl(Op);
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StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
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SDValue Val = SN->getValue();
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MVT Ty = ty(Val);
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bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1);
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if (DoCast) {
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SDValue TC = DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, Val);
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SDValue NS = DAG.getStore(SN->getChain(), dl, TC, SN->getBasePtr(),
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SN->getMemOperand());
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if (SN->isIndexed()) {
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NS = DAG.getIndexedStore(NS, dl, SN->getBasePtr(), SN->getOffset(),
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SN->getAddressingMode());
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}
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SN = cast<StoreSDNode>(NS.getNode());
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}
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unsigned ClaimAlign = SN->getAlignment();
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SDValue Ptr = SN->getBasePtr();
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const SDLoc &dl(Op);
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validateConstPtrAlignment(Ptr, dl, ClaimAlign);
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MVT StoreTy = SN->getMemoryVT().getSimpleVT();
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unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy);
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if (ClaimAlign < NeedAlign)
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return expandUnalignedStore(SN, DAG);
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return Op;
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return SDValue(SN, 0);
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}
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SDValue
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276
test/CodeGen/Hexagon/isel-memory-vNi1.ll
Normal file
276
test/CodeGen/Hexagon/isel-memory-vNi1.ll
Normal file
@ -0,0 +1,276 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon < %s | FileCheck %s
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define i64 @f0(<8 x i1>* %a0, <8 x i8> %a1) #0 {
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; CHECK-LABEL: f0:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = memub(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5:4 = combine(#0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = r0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1:0 = vmux(p0,r3:2,r5:4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = load <8 x i1>, <8 x i1>* %a0, align 1
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%v1 = select <8 x i1> %v0, <8 x i8> %a1, <8 x i8> zeroinitializer
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%v2 = bitcast <8 x i8> %v1 to i64
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ret i64 %v2
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}
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define i32 @f1(<4 x i1>* %a0, <4 x i8> %a1) #0 {
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; CHECK-LABEL: f1:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = memub(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = #0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5:4 = vsxtbh(r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3:2 = vsxtbh(r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = r0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1:0 = vmux(p0,r5:4,r3:2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = vtrunehb(r1:0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = load <4 x i1>, <4 x i1>* %a0, align 1
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%v1 = select <4 x i1> %v0, <4 x i8> %a1, <4 x i8> zeroinitializer
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%v2 = bitcast <4 x i8> %v1 to i32
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ret i32 %v2
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}
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define i16 @f2(<2 x i1>* %a0, <2 x i8> %a1) #0 {
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; CHECK-LABEL: f2:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = memub(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p1 = tstbit(r0,#4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = r0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = mux(p1,r3,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = mux(p0,r2,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = insert(r1,#24,#8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = load <2 x i1>, <2 x i1>* %a0, align 1
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%v1 = select <2 x i1> %v0, <2 x i8> %a1, <2 x i8> zeroinitializer
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%v2 = bitcast <2 x i8> %v1 to i16
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ret i16 %v2
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}
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define i8 @f3(<1 x i1>* %a0, <1 x i8> %a1) #0 {
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; CHECK-LABEL: f3:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = memub(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = r0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = mux(p0,r1,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = load <1 x i1>, <1 x i1>* %a0, align 1
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%v1 = select <1 x i1> %v0, <1 x i8> %a1, <1 x i8> zeroinitializer
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%v2 = bitcast <1 x i8> %v1 to i8
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ret i8 %v2
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}
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define void @f4(<8 x i1>* %a0, i64 %a1) #0 {
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; CHECK-LABEL: f4:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r5:4 = combine(#0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = vcmpb.eq(r3:2,r5:4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = mux(p0,#0,#1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memb(r0+#0) = r1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = bitcast i64 %a1 to <8 x i8>
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%v1 = icmp ne <8 x i8> %v0, zeroinitializer
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store <8 x i1> %v1, <8 x i1>* %a0, align 1
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ret void
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}
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define void @f5(<4 x i1>* %a0, i32 %a1) #0 {
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; CHECK-LABEL: f5:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = #0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5:4 = vsxtbh(r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3:2 = vsxtbh(r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = vcmph.eq(r5:4,r3:2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = mux(p0,#0,#1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memb(r0+#0) = r1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = bitcast i32 %a1 to <4 x i8>
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%v1 = icmp ne <4 x i8> %v0, zeroinitializer
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store <4 x i1> %v1, <4 x i1>* %a0, align 1
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ret void
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}
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define void @f6(<2 x i1>* %a0, i16 %a1) #0 {
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; CHECK-LABEL: f6:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = extractu(r1,#8,#8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = #255
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p1 = !bitsclr(r1,r3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.eq(r2,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (p0) r2 = #0
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = mux(p1,#8,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = mux(p1,#2,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = setbit(r1,#2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r6 = setbit(r3,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) r2 = #128
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r4 = mux(p0,#0,#32)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p1) r5 = add(r1,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = setbit(r2,#6)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p1) r6 = add(r3,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r3 = setbit(r4,#4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 = or(r6,r5)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) r2 = add(r1,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (!p0) r4 = add(r3,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r5 |= or(r4,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = r5
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = mux(p0,#1,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memb(r0+#0) = r1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = bitcast i16 %a1 to <2 x i8>
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%v1 = icmp ne <2 x i8> %v0, zeroinitializer
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store <2 x i1> %v1, <2 x i1>* %a0, align 1
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ret void
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}
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define void @f7(<1 x i1>* %a0, i8 %a1) #0 {
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; CHECK-LABEL: f7:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = #255
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = !bitsclr(r1,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = mux(p0,#1,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: memb(r0+#0) = r1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = bitcast i8 %a1 to <1 x i8>
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%v1 = icmp ne <1 x i8> %v0, zeroinitializer
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store <1 x i1> %v1, <1 x i1>* %a0, align 1
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ret void
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}
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attributes #0 = { nounwind "target-features"="-packets" }
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