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[AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).

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This change only effects codegen when the constant is -3.

llvm-svn: 231085
This commit is contained in:
Chad Rosier 2015-03-03 17:31:01 +00:00
parent 8d1b74869c
commit c6fa32cc2a
2 changed files with 10 additions and 11 deletions
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18
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -6895,6 +6895,15 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
N->getOperand(0));
}
} else {
// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
APInt VNP1 = -Value + 1;
if (VNP1.isPowerOf2()) {
SDValue ShiftedVal =
DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
DAG.getConstant(VNP1.logBase2(), MVT::i64));
return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
ShiftedVal);
}
// (mul x, -(2^N + 1)) => - (add (shl x, N), x)
APInt VNM1 = -Value - 1;
if (VNM1.isPowerOf2()) {
@ -6905,15 +6914,6 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
}
// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
APInt VNP1 = -Value + 1;
if (VNP1.isPowerOf2()) {
SDValue ShiftedVal =
DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
DAG.getConstant(VNP1.logBase2(), MVT::i64));
return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
ShiftedVal);
}
}
}
return SDValue();

3
test/CodeGen/AArch64/mul_pow2.ll
View File

@ -74,8 +74,7 @@ define i32 @ntest2(i32 %x) {
define i32 @ntest3(i32 %x) {
; CHECK-LABEL: ntest3
; CHECK: add {{w[0-9]+}}, w0, w0, lsl #1
; CHECK: neg w0, {{w[0-9]+}}
; CHECK: sub w0, w0, w0, lsl #2
%mul = mul nsw i32 %x, -3
ret i32 %mul