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Zap some junk from the ARM instruction descriptions.

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llvm-svn: 139575
This commit is contained in:
Eli Friedman 2011-09-13 02:29:58 +00:00
parent 2cc8637af2
commit c6ff621dc5
4 changed files with 0 additions and 67 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -234,8 +234,6 @@ namespace {
const { return 0; }
unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
unsigned Op) const { return 0; }
unsigned getMsbOpValue(const MachineInstr &MI,
unsigned Op) const { return 0; }
unsigned getSsatBitPosValue(const MachineInstr &MI,
unsigned Op) const { return 0; }
uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)

31
lib/Target/ARM/ARMInstrInfo.td
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@ -578,18 +578,6 @@ def bf_inv_mask_imm : Operand<i32>,
let ParserMatchClass = BitfieldAsmOperand;
}
/// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
return isInt<5>(Imm);
}]>;
/// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
def width_imm : Operand<i32>, ImmLeaf<i32, [{
return Imm > 0 && Imm <= 32;
}] > {
let EncoderMethod = "getMsbOpValue";
}
def imm1_32_XFORM: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
}]>;
@ -3411,25 +3399,6 @@ def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
let Inst{3-0} = Rn;
}
// GNU as only supports this form of bfi (w/ 4 arguments)
let isAsmParserOnly = 1 in
def BFI4p : I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn,
lsb_pos_imm:$lsb, width_imm:$width),
AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
"bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
[]>, Requires<[IsARM, HasV6T2]> {
bits<4> Rd;
bits<4> Rn;
bits<5> lsb;
bits<5> width;
let Inst{27-21} = 0b0111110;
let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
let Inst{15-12} = Rd;
let Inst{11-7} = lsb;
let Inst{20-16} = width; // Custom encoder => lsb+width-1
let Inst{3-0} = Rn;
}
def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
"mvn", "\t$Rd, $Rm",
[(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {

20
lib/Target/ARM/ARMInstrThumb2.td
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@ -2240,26 +2240,6 @@ let Constraints = "$src = $Rd" in {
let msb{4-0} = imm{9-5};
let lsb{4-0} = imm{4-0};
}
// GNU as only supports this form of bfi (w/ 4 arguments)
let isAsmParserOnly = 1 in
def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
(ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
width_imm:$width),
IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
[]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0; // should be 0.
let Inst{25} = 1;
let Inst{24-20} = 0b10110;
let Inst{15} = 0;
let Inst{5} = 0; // should be 0.
bits<5> lsbit;
bits<5> width;
let msb{4-0} = width; // Custom encoder => lsb+width-1
let lsb{4-0} = lsbit;
}
}
defm t2ORN : T2I_bin_irs<0b0011, "orn",

14
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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@ -283,9 +283,6 @@ public:
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
@ -1304,17 +1301,6 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
return lsb | (msb << 5);
}
unsigned ARMMCCodeEmitter::
getMsbOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const {
// MSB - 5 bits.
uint32_t lsb = MI.getOperand(Op-1).getImm();
uint32_t width = MI.getOperand(Op).getImm();
uint32_t msb = lsb+width-1;
assert (width != 0 && msb < 32 && "Illegal bit width!");
return msb;
}
unsigned ARMMCCodeEmitter::
getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const {