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Teach legalize to deal with targets that don't support some SEXTLOAD/ZEXTLOADs
llvm-svn: 21212
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parent
380f2b2963
commit
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@ -442,13 +442,19 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case ISD::EXTLOAD:
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case ISD::SEXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::ZEXTLOAD: {
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType();
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switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
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case TargetLowering::Promote:
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal:
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if (Tmp1 != Node->getOperand(0) ||
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Tmp2 != Node->getOperand(1))
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2,
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cast<MVTSDNode>(Node)->getExtraValueType());
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
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Tmp1, Tmp2, SrcVT);
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else
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Result = SDOperand(Node, 0);
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@ -457,7 +463,26 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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AddLegalizedOperand(SDOperand(Node, 0), Result);
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AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
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return Result.getValue(Op.ResNo);
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break;
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case TargetLowering::Expand:
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assert(Node->getOpcode() != ISD::EXTLOAD &&
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"EXTLOAD should always be supported!");
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// Turn the unsupported load into an EXTLOAD followed by an explicit
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// zero/sign extend inreg.
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Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
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Tmp1, Tmp2, SrcVT);
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unsigned ExtOp = Node->getOpcode() == ISD::SEXTLOAD ?
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ISD::SIGN_EXTEND_INREG : ISD::ZERO_EXTEND_INREG;
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SDOperand ValRes = DAG.getNode(ExtOp, Result.getValueType(),
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Result, SrcVT);
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AddLegalizedOperand(SDOperand(Node, 0), ValRes);
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AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
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if (Op.ResNo)
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return Result.getValue(1);
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return ValRes;
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}
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assert(0 && "Unreachable");
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}
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case ISD::EXTRACT_ELEMENT:
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// Get both the low and high parts.
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ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
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