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[SelectionDAGBuilder] Update signature of getRegsAndSizes().

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The mapping between registers and relative size has been updated to
use TypeSize to account for the size of scalable EVTs.

The patch is a NFCI, if not for the fact that with this change the
function `getUnderlyingArgRegs` does not raise a warning for implicit
conversion of `TypeSize` to `unsigned` when generating machine code
from the test added to the patch.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D92096
This commit is contained in:
Francesco Petrogalli 2020-11-30 17:30:11 +00:00 committed by Joe Ellis
parent 3c6cfc8543
commit c7518fb829
3 changed files with 38 additions and 8 deletions
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14
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -980,14 +980,14 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
}
}
SmallVector<std::pair<unsigned, unsigned>, 4>
SmallVector<std::pair<unsigned, TypeSize>, 4>
RegsForValue::getRegsAndSizes() const {
SmallVector<std::pair<unsigned, unsigned>, 4> OutVec;
SmallVector<std::pair<unsigned, TypeSize>, 4> OutVec;
unsigned I = 0;
for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
unsigned RegCount = std::get<0>(CountAndVT);
MVT RegisterVT = std::get<1>(CountAndVT);
unsigned RegisterSize = RegisterVT.getSizeInBits();
TypeSize RegisterSize = RegisterVT.getSizeInBits();
for (unsigned E = I + RegCount; I != E; ++I)
OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
}
@ -5317,7 +5317,7 @@ static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
// getUnderlyingArgRegs - Find underlying registers used for a truncated,
// bitcasted, or split argument. Returns a list of <Register, size in bits>
static void
getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, TypeSize>> &Regs,
const SDValue &N) {
switch (N.getOpcode()) {
case ISD::CopyFromReg: {
@ -5428,7 +5428,7 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
if (FI != std::numeric_limits<int>::max())
Op = MachineOperand::CreateFI(FI);
SmallVector<std::pair<unsigned, unsigned>, 8> ArgRegsAndSizes;
SmallVector<std::pair<unsigned, TypeSize>, 8> ArgRegsAndSizes;
if (!Op && N.getNode()) {
getUnderlyingArgRegs(ArgRegsAndSizes, N);
Register Reg;
@ -5458,8 +5458,8 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
if (!Op) {
// Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg
auto splitMultiRegDbgValue
= [&](ArrayRef<std::pair<unsigned, unsigned>> SplitRegs) {
auto splitMultiRegDbgValue = [&](ArrayRef<std::pair<unsigned, TypeSize>>
SplitRegs) {
unsigned Offset = 0;
for (auto RegAndSize : SplitRegs) {
// If the expression is already a fragment, the current register

2
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -895,7 +895,7 @@ struct RegsForValue {
}
/// Return a list of registers and their sizes.
SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const;
SmallVector<std::pair<unsigned, TypeSize>, 4> getRegsAndSizes() const;
};
} // end namespace llvm

30
test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll Normal file
View File

@ -0,0 +1,30 @@
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
; If this check fails please read
; clang/test/CodeGen/aarch64-sve-intrinsics/README for instructions on
; how to resolve it.
; WARN-NOT: warning
; CHECK-LABEL: do_something:
define <vscale x 2 x double> @do_something(<vscale x 2 x double> %vx) {
entry:
call void @llvm.dbg.value(metadata <vscale x 2 x double> %vx, metadata !3, metadata !DIExpression()), !dbg !5
%0 = tail call <vscale x 2 x double> @f(<vscale x 2 x double> %vx)
ret <vscale x 2 x double> %0
}
declare <vscale x 2 x double> @f(<vscale x 2 x double>)
declare void @llvm.dbg.value(metadata, metadata, metadata)
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1)
!1 = !DIFile(filename: "file.c", directory: "/")
!2 = !{i32 2, !"Debug Info Version", i32 3}
!3 = !DILocalVariable(scope: !4)
!4 = distinct !DISubprogram(unit: !0)
!5 = !DILocation(scope: !4)