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https://github.com/RPCS3/llvm-mirror.git
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[CodeGen] Fix inconsistent declaration parameter name
llvm-svn: 337200
This commit is contained in:
parent
f5197c1fcd
commit
c76988a0c0
@ -338,7 +338,7 @@ public:
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/// global value is specified, and if that global has an explicit alignment
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/// global value is specified, and if that global has an explicit alignment
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/// requested, it will override the alignment request if required for
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/// requested, it will override the alignment request if required for
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/// correctness.
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/// correctness.
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void EmitAlignment(unsigned NumBits, const GlobalObject *GO = nullptr) const;
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void EmitAlignment(unsigned NumBits, const GlobalObject *GV = nullptr) const;
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/// Lower the specified LLVM Constant to an MCExpr.
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/// Lower the specified LLVM Constant to an MCExpr.
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virtual const MCExpr *lowerConstant(const Constant *CV);
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virtual const MCExpr *lowerConstant(const Constant *CV);
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@ -646,7 +646,7 @@ private:
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void EmitXXStructorList(const DataLayout &DL, const Constant *List,
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void EmitXXStructorList(const DataLayout &DL, const Constant *List,
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bool isCtor);
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bool isCtor);
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GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy &C);
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GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy &S);
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/// Emit GlobalAlias or GlobalIFunc.
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/// Emit GlobalAlias or GlobalIFunc.
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void emitGlobalIndirectSymbol(Module &M, const GlobalIndirectSymbol &GIS);
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void emitGlobalIndirectSymbol(Module &M, const GlobalIndirectSymbol &GIS);
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void setupCodePaddingContext(const MachineBasicBlock &MBB,
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void setupCodePaddingContext(const MachineBasicBlock &MBB,
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@ -58,7 +58,7 @@ using CreateCmpXchgInstFun =
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/// [...]
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/// [...]
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///
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///
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/// Returns true if the containing function was modified.
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/// Returns true if the containing function was modified.
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bool expandAtomicRMWToCmpXchg(AtomicRMWInst *AI, CreateCmpXchgInstFun Factory);
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bool expandAtomicRMWToCmpXchg(AtomicRMWInst *AI, CreateCmpXchgInstFun CreateCmpXchg);
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} // end namespace llvm
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} // end namespace llvm
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@ -1379,7 +1379,7 @@ class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
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const TargetLoweringBase *getTLI() const { return TLI; }
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const TargetLoweringBase *getTLI() const { return TLI; }
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public:
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public:
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explicit BasicTTIImpl(const TargetMachine *ST, const Function &F);
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explicit BasicTTIImpl(const TargetMachine *TM, const Function &F);
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};
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};
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} // end namespace llvm
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} // end namespace llvm
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@ -304,7 +304,7 @@ public:
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/// CheckReturn - Analyze the return values of a function, returning
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/// CheckReturn - Analyze the return values of a function, returning
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/// true if the return can be performed without sret-demotion, and
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/// true if the return can be performed without sret-demotion, and
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/// false otherwise.
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/// false otherwise.
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bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
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bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn);
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CCAssignFn Fn);
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/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
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/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
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@ -190,7 +190,7 @@ public:
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uint64_t getValue() const { return Integer; }
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uint64_t getValue() const { return Integer; }
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void setValue(uint64_t Val) { Integer = Val; }
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void setValue(uint64_t Val) { Integer = Val; }
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void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
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void EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const;
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unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
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unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
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void print(raw_ostream &O) const;
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void print(raw_ostream &O) const;
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@ -868,7 +868,7 @@ public:
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return dwarf::DW_FORM_block;
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return dwarf::DW_FORM_block;
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}
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}
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void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
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void EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const;
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unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
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unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
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void print(raw_ostream &O) const;
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void print(raw_ostream &O) const;
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@ -899,7 +899,7 @@ public:
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return dwarf::DW_FORM_block;
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return dwarf::DW_FORM_block;
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}
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}
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void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
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void EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const;
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unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
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unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
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void print(raw_ostream &O) const;
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void print(raw_ostream &O) const;
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@ -280,7 +280,7 @@ public:
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/// This is a wrapper around getRegForValue that also takes care of
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/// This is a wrapper around getRegForValue that also takes care of
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/// truncating or sign-extending the given getelementptr index value.
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/// truncating or sign-extending the given getelementptr index value.
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std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
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std::pair<unsigned, bool> getRegForGEPIndex(const Value *Idx);
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/// We're checking to see if we can fold \p LI into \p FoldInst. Note
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/// We're checking to see if we can fold \p LI into \p FoldInst. Note
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/// that we could have a sequence where multiple LLVM IR instructions are
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/// that we could have a sequence where multiple LLVM IR instructions are
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@ -439,7 +439,7 @@ protected:
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/// Emit a MachineInstr with a single immediate operand, and a result
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/// Emit a MachineInstr with a single immediate operand, and a result
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/// register in the given register class.
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/// register in the given register class.
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unsigned fastEmitInst_i(unsigned MachineInstrOpcode,
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unsigned fastEmitInst_i(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC, uint64_t Imm);
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const TargetRegisterClass *RC, uint64_t Imm);
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/// Emit a MachineInstr for an extract_subreg from a specified index of
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/// Emit a MachineInstr for an extract_subreg from a specified index of
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@ -453,7 +453,7 @@ protected:
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/// Emit an unconditional branch to the given block, unless it is the
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/// Emit an unconditional branch to the given block, unless it is the
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/// immediate (fall-through) successor, and update the CFG.
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/// immediate (fall-through) successor, and update the CFG.
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void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL);
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void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc);
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/// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
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/// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
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/// and adds TrueMBB and FalseMBB to the successor list.
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/// and adds TrueMBB and FalseMBB to the successor list.
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@ -508,7 +508,7 @@ protected:
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CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
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CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
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bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
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bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
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bool lowerCallTo(const CallInst *CI, const char *SymbolName,
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bool lowerCallTo(const CallInst *CI, const char *SymName,
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unsigned NumArgs);
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unsigned NumArgs);
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bool lowerCallTo(CallLoweringInfo &CLI);
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bool lowerCallTo(CallLoweringInfo &CLI);
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@ -532,11 +532,11 @@ protected:
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bool selectGetElementPtr(const User *I);
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bool selectGetElementPtr(const User *I);
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bool selectStackmap(const CallInst *I);
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bool selectStackmap(const CallInst *I);
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bool selectPatchpoint(const CallInst *I);
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bool selectPatchpoint(const CallInst *I);
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bool selectCall(const User *Call);
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bool selectCall(const User *I);
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bool selectIntrinsicCall(const IntrinsicInst *II);
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bool selectIntrinsicCall(const IntrinsicInst *II);
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bool selectBitCast(const User *I);
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bool selectBitCast(const User *I);
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bool selectCast(const User *I, unsigned Opcode);
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bool selectCast(const User *I, unsigned Opcode);
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bool selectExtractValue(const User *I);
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bool selectExtractValue(const User *U);
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bool selectInsertValue(const User *I);
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bool selectInsertValue(const User *I);
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bool selectXRayCustomEvent(const CallInst *II);
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bool selectXRayCustomEvent(const CallInst *II);
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bool selectXRayTypedEvent(const CallInst *II);
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bool selectXRayTypedEvent(const CallInst *II);
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@ -123,7 +123,7 @@ protected:
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}
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}
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template <typename FuncInfoTy>
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template <typename FuncInfoTy>
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void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL,
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void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL,
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const FuncInfoTy &FuncInfo) const;
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const FuncInfoTy &FuncInfo) const;
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/// Invoke Handler::assignArg on each of the given \p Args and then use
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/// Invoke Handler::assignArg on each of the given \p Args and then use
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@ -131,7 +131,7 @@ protected:
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///
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///
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/// \return True if everything has succeeded, false otherwise.
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/// \return True if everything has succeeded, false otherwise.
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bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef<ArgInfo> Args,
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bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef<ArgInfo> Args,
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ValueHandler &Callback) const;
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ValueHandler &Handler) const;
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public:
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public:
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CallLowering(const TargetLowering *TLI) : TLI(TLI) {}
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CallLowering(const TargetLowering *TLI) : TLI(TLI) {}
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@ -210,7 +210,7 @@ private:
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/// Translate an LLVM string intrinsic (memcpy, memset, ...).
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/// Translate an LLVM string intrinsic (memcpy, memset, ...).
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bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
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bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
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unsigned Intrinsic);
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unsigned ID);
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void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
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void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
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@ -110,7 +110,7 @@ private:
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/// the given Type (which implies the number of blocks needed). The generic
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/// the given Type (which implies the number of blocks needed). The generic
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/// registers created are appended to Ops, starting at bit 0 of Reg.
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/// registers created are appended to Ops, starting at bit 0 of Reg.
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void extractParts(unsigned Reg, LLT Ty, int NumParts,
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void extractParts(unsigned Reg, LLT Ty, int NumParts,
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SmallVectorImpl<unsigned> &Ops);
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SmallVectorImpl<unsigned> &VRegs);
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MachineRegisterInfo &MRI;
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MachineRegisterInfo &MRI;
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const LegalizerInfo &LI;
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const LegalizerInfo &LI;
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@ -95,7 +95,7 @@ protected:
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return MIB->getOperand(0).getReg();
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return MIB->getOperand(0).getReg();
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}
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}
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void validateBinaryOp(unsigned Dst, unsigned Src0, unsigned Src1);
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void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1);
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public:
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public:
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/// Some constructors for easy use.
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/// Some constructors for easy use.
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@ -424,7 +424,7 @@ public:
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/// \pre setBasicBlock or setMI must have been called.
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/// \pre setBasicBlock or setMI must have been called.
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///
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///
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/// \return a MachineInstrBuilder for the newly created instruction.
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/// \return a MachineInstrBuilder for the newly created instruction.
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MachineInstrBuilder buildBr(MachineBasicBlock &BB);
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MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
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/// Build and insert G_BRCOND \p Tst, \p Dest
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/// Build and insert G_BRCOND \p Tst, \p Dest
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///
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///
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@ -438,7 +438,7 @@ public:
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/// depend on bit 0 (for now).
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/// depend on bit 0 (for now).
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///
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///
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/// \return The newly created instruction.
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/// \return The newly created instruction.
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MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &BB);
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MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
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/// Build and insert G_BRINDIRECT \p Tgt
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/// Build and insert G_BRINDIRECT \p Tgt
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///
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///
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@ -558,7 +558,7 @@ public:
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template <typename DstType> MachineInstrBuilder buildUndef(DstType &&Res) {
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template <typename DstType> MachineInstrBuilder buildUndef(DstType &&Res) {
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return buildUndef(getDestFromArg(Res));
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return buildUndef(getDestFromArg(Res));
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}
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}
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MachineInstrBuilder buildUndef(unsigned Dst);
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MachineInstrBuilder buildUndef(unsigned Res);
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/// Build and insert instructions to put \p Ops together at the specified p
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/// Build and insert instructions to put \p Ops together at the specified p
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/// Indices to form a larger register.
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/// Indices to form a larger register.
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@ -42,7 +42,7 @@ private:
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public:
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public:
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RegisterBank(unsigned ID, const char *Name, unsigned Size,
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RegisterBank(unsigned ID, const char *Name, unsigned Size,
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const uint32_t *ContainedRegClasses, unsigned NumRegClasses);
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const uint32_t *CoveredClasses, unsigned NumRegClasses);
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/// Get the identifier of this register bank.
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/// Get the identifier of this register bank.
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unsigned getID() const { return ID; }
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unsigned getID() const { return ID; }
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@ -27,7 +27,7 @@ namespace llvm {
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LatencyPriorityQueue *PQ;
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LatencyPriorityQueue *PQ;
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explicit latency_sort(LatencyPriorityQueue *pq) : PQ(pq) {}
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explicit latency_sort(LatencyPriorityQueue *pq) : PQ(pq) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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bool operator()(const SUnit* LHS, const SUnit* RHS) const;
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};
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};
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class LatencyPriorityQueue : public SchedulingPriorityQueue {
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class LatencyPriorityQueue : public SchedulingPriorityQueue {
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@ -92,7 +92,7 @@ namespace llvm {
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// successor nodes that have a single unscheduled predecessor. If so, that
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// successor nodes that have a single unscheduled predecessor. If so, that
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// single predecessor has a higher priority, since scheduling it will make
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// single predecessor has a higher priority, since scheduling it will make
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// the node available.
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// the node available.
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void scheduledNode(SUnit *Node) override;
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void scheduledNode(SUnit *SU) override;
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private:
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private:
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void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
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void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
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@ -326,7 +326,7 @@ namespace llvm {
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/// createDeadDef - Make sure the range has a value defined at Def.
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/// createDeadDef - Make sure the range has a value defined at Def.
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/// If one already exists, return it. Otherwise allocate a new value and
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/// If one already exists, return it. Otherwise allocate a new value and
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/// add liveness for a dead def.
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/// add liveness for a dead def.
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VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator);
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VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc);
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/// Create a def of value @p VNI. Return @p VNI. If there already exists
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/// Create a def of value @p VNI. Return @p VNI. If there already exists
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/// a definition at VNI->def, the value defined there must be @p VNI.
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/// a definition at VNI->def, the value defined there must be @p VNI.
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@ -454,7 +454,7 @@ namespace llvm {
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/// overlapsFrom - Return true if the intersection of the two live ranges
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/// overlapsFrom - Return true if the intersection of the two live ranges
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/// is not empty. The specified iterator is a hint that we can begin
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/// is not empty. The specified iterator is a hint that we can begin
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/// scanning the Other range starting at I.
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/// scanning the Other range starting at I.
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bool overlapsFrom(const LiveRange &Other, const_iterator I) const;
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bool overlapsFrom(const LiveRange &Other, const_iterator StartPos) const;
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/// Returns true if all segments of the @p Other live range are completely
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/// Returns true if all segments of the @p Other live range are completely
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/// covered by this live range.
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/// covered by this live range.
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@ -482,7 +482,7 @@ namespace llvm {
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/// @p Use, return {nullptr, false}. If there is an "undef" before @p Use,
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/// @p Use, return {nullptr, false}. If there is an "undef" before @p Use,
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/// return {nullptr, true}.
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/// return {nullptr, true}.
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std::pair<VNInfo*,bool> extendInBlock(ArrayRef<SlotIndex> Undefs,
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std::pair<VNInfo*,bool> extendInBlock(ArrayRef<SlotIndex> Undefs,
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SlotIndex StartIdx, SlotIndex Use);
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SlotIndex StartIdx, SlotIndex Kill);
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/// Simplified version of the above "extendInBlock", which assumes that
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/// Simplified version of the above "extendInBlock", which assumes that
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/// no register lanes are undefined by <def,read-undef> operands.
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/// no register lanes are undefined by <def,read-undef> operands.
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@ -791,7 +791,7 @@ namespace llvm {
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/// L00E0 and L0010 and the L000F lane into L0007 and L0008. The Mod
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/// L00E0 and L0010 and the L000F lane into L0007 and L0008. The Mod
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/// function will be applied to the L0010 and L0008 subranges.
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/// function will be applied to the L0010 and L0008 subranges.
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void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask,
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void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask,
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std::function<void(LiveInterval::SubRange&)> Mod);
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std::function<void(LiveInterval::SubRange&)> Apply);
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bool operator<(const LiveInterval& other) const {
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bool operator<(const LiveInterval& other) const {
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const SlotIndex &thisIndex = beginIndex();
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const SlotIndex &thisIndex = beginIndex();
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@ -154,7 +154,7 @@ public:
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unsigned MaxInterferingRegs = std::numeric_limits<unsigned>::max());
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unsigned MaxInterferingRegs = std::numeric_limits<unsigned>::max());
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// Was this virtual register visited during collectInterferingVRegs?
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// Was this virtual register visited during collectInterferingVRegs?
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bool isSeenInterference(LiveInterval *VReg) const;
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bool isSeenInterference(LiveInterval *VirtReg) const;
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// Did collectInterferingVRegs collect all interferences?
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// Did collectInterferingVRegs collect all interferences?
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bool seenAllInterferences() const { return SeenAllInterferences; }
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bool seenAllInterferences() const { return SeenAllInterferences; }
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@ -105,7 +105,7 @@ class VirtRegMap;
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/// Calculate the spill weight to assign to a single instruction.
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/// Calculate the spill weight to assign to a single instruction.
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static float getSpillWeight(bool isDef, bool isUse,
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static float getSpillWeight(bool isDef, bool isUse,
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const MachineBlockFrequencyInfo *MBFI,
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const MachineBlockFrequencyInfo *MBFI,
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const MachineInstr &Instr);
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const MachineInstr &MI);
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/// Calculate the spill weight to assign to a single instruction.
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/// Calculate the spill weight to assign to a single instruction.
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static float getSpillWeight(bool isDef, bool isUse,
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static float getSpillWeight(bool isDef, bool isUse,
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||||||
|
@ -38,7 +38,7 @@ void printMIR(raw_ostream &OS, const MachineFunction &MF);
|
|||||||
/// this funciton and the parser will use this function to construct a list if
|
/// this funciton and the parser will use this function to construct a list if
|
||||||
/// it is missing.
|
/// it is missing.
|
||||||
void guessSuccessors(const MachineBasicBlock &MBB,
|
void guessSuccessors(const MachineBasicBlock &MBB,
|
||||||
SmallVectorImpl<MachineBasicBlock*> &Successors,
|
SmallVectorImpl<MachineBasicBlock*> &Result,
|
||||||
bool &IsFallthrough);
|
bool &IsFallthrough);
|
||||||
|
|
||||||
} // end namespace llvm
|
} // end namespace llvm
|
||||||
|
@ -58,7 +58,7 @@ private:
|
|||||||
public:
|
public:
|
||||||
void addNodeToList(MachineInstr *N);
|
void addNodeToList(MachineInstr *N);
|
||||||
void removeNodeFromList(MachineInstr *N);
|
void removeNodeFromList(MachineInstr *N);
|
||||||
void transferNodesFromList(ilist_traits &OldList, instr_iterator First,
|
void transferNodesFromList(ilist_traits &FromList, instr_iterator First,
|
||||||
instr_iterator Last);
|
instr_iterator Last);
|
||||||
void deleteNode(MachineInstr *MI);
|
void deleteNode(MachineInstr *MI);
|
||||||
};
|
};
|
||||||
|
@ -81,8 +81,8 @@ template <> struct ilist_alloc_traits<MachineBasicBlock> {
|
|||||||
};
|
};
|
||||||
|
|
||||||
template <> struct ilist_callback_traits<MachineBasicBlock> {
|
template <> struct ilist_callback_traits<MachineBasicBlock> {
|
||||||
void addNodeToList(MachineBasicBlock* MBB);
|
void addNodeToList(MachineBasicBlock* N);
|
||||||
void removeNodeFromList(MachineBasicBlock* MBB);
|
void removeNodeFromList(MachineBasicBlock* N);
|
||||||
|
|
||||||
template <class Iterator>
|
template <class Iterator>
|
||||||
void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator) {
|
void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator) {
|
||||||
@ -366,7 +366,7 @@ public:
|
|||||||
using VariableDbgInfoMapTy = SmallVector<VariableDbgInfo, 4>;
|
using VariableDbgInfoMapTy = SmallVector<VariableDbgInfo, 4>;
|
||||||
VariableDbgInfoMapTy VariableDbgInfos;
|
VariableDbgInfoMapTy VariableDbgInfos;
|
||||||
|
|
||||||
MachineFunction(const Function &F, const TargetMachine &TM,
|
MachineFunction(const Function &F, const TargetMachine &Target,
|
||||||
const TargetSubtargetInfo &STI, unsigned FunctionNum,
|
const TargetSubtargetInfo &STI, unsigned FunctionNum,
|
||||||
MachineModuleInfo &MMI);
|
MachineModuleInfo &MMI);
|
||||||
MachineFunction(const MachineFunction &) = delete;
|
MachineFunction(const MachineFunction &) = delete;
|
||||||
@ -809,7 +809,7 @@ public:
|
|||||||
void addCleanup(MachineBasicBlock *LandingPad);
|
void addCleanup(MachineBasicBlock *LandingPad);
|
||||||
|
|
||||||
void addSEHCatchHandler(MachineBasicBlock *LandingPad, const Function *Filter,
|
void addSEHCatchHandler(MachineBasicBlock *LandingPad, const Function *Filter,
|
||||||
const BlockAddress *RecoverLabel);
|
const BlockAddress *RecoverBA);
|
||||||
|
|
||||||
void addSEHCleanupHandler(MachineBasicBlock *LandingPad,
|
void addSEHCleanupHandler(MachineBasicBlock *LandingPad,
|
||||||
const Function *Cleanup);
|
const Function *Cleanup);
|
||||||
|
@ -141,7 +141,7 @@ private:
|
|||||||
/// This constructor create a MachineInstr and add the implicit operands.
|
/// This constructor create a MachineInstr and add the implicit operands.
|
||||||
/// It reserves space for number of operands specified by
|
/// It reserves space for number of operands specified by
|
||||||
/// MCInstrDesc. An explicit DebugLoc is supplied.
|
/// MCInstrDesc. An explicit DebugLoc is supplied.
|
||||||
MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
|
MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
|
||||||
bool NoImp = false);
|
bool NoImp = false);
|
||||||
|
|
||||||
// MachineInstrs are pool-allocated and owned by MachineFunction.
|
// MachineInstrs are pool-allocated and owned by MachineFunction.
|
||||||
@ -1321,7 +1321,7 @@ public:
|
|||||||
|
|
||||||
/// Erase an operand from an instruction, leaving it with one
|
/// Erase an operand from an instruction, leaving it with one
|
||||||
/// fewer operand than it started with.
|
/// fewer operand than it started with.
|
||||||
void RemoveOperand(unsigned i);
|
void RemoveOperand(unsigned OpNo);
|
||||||
|
|
||||||
/// Add a MachineMemOperand to the machine instruction.
|
/// Add a MachineMemOperand to the machine instruction.
|
||||||
/// This function should be used only occasionally. The setMemRefs function
|
/// This function should be used only occasionally. The setMemRefs function
|
||||||
|
@ -184,7 +184,7 @@ public:
|
|||||||
/// atomic operations the atomic ordering requirements when store does not
|
/// atomic operations the atomic ordering requirements when store does not
|
||||||
/// occur must also be specified.
|
/// occur must also be specified.
|
||||||
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
|
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
|
||||||
uint64_t base_alignment,
|
uint64_t a,
|
||||||
const AAMDNodes &AAInfo = AAMDNodes(),
|
const AAMDNodes &AAInfo = AAMDNodes(),
|
||||||
const MDNode *Ranges = nullptr,
|
const MDNode *Ranges = nullptr,
|
||||||
SyncScope::ID SSID = SyncScope::System,
|
SyncScope::ID SSID = SyncScope::System,
|
||||||
|
@ -56,7 +56,7 @@ public:
|
|||||||
/// MachineSSAUpdater constructor. If InsertedPHIs is specified, it will be
|
/// MachineSSAUpdater constructor. If InsertedPHIs is specified, it will be
|
||||||
/// filled in with all PHI Nodes created by rewriting.
|
/// filled in with all PHI Nodes created by rewriting.
|
||||||
explicit MachineSSAUpdater(MachineFunction &MF,
|
explicit MachineSSAUpdater(MachineFunction &MF,
|
||||||
SmallVectorImpl<MachineInstr*> *InsertedPHIs = nullptr);
|
SmallVectorImpl<MachineInstr*> *NewPHI = nullptr);
|
||||||
MachineSSAUpdater(const MachineSSAUpdater &) = delete;
|
MachineSSAUpdater(const MachineSSAUpdater &) = delete;
|
||||||
MachineSSAUpdater &operator=(const MachineSSAUpdater &) = delete;
|
MachineSSAUpdater &operator=(const MachineSSAUpdater &) = delete;
|
||||||
~MachineSSAUpdater();
|
~MachineSSAUpdater();
|
||||||
|
@ -40,7 +40,7 @@ std::unique_ptr<Module>
|
|||||||
splitCodeGen(std::unique_ptr<Module> M, ArrayRef<raw_pwrite_stream *> OSs,
|
splitCodeGen(std::unique_ptr<Module> M, ArrayRef<raw_pwrite_stream *> OSs,
|
||||||
ArrayRef<llvm::raw_pwrite_stream *> BCOSs,
|
ArrayRef<llvm::raw_pwrite_stream *> BCOSs,
|
||||||
const std::function<std::unique_ptr<TargetMachine>()> &TMFactory,
|
const std::function<std::unique_ptr<TargetMachine>()> &TMFactory,
|
||||||
TargetMachine::CodeGenFileType FT = TargetMachine::CGFT_ObjectFile,
|
TargetMachine::CodeGenFileType FileType = TargetMachine::CGFT_ObjectFile,
|
||||||
bool PreserveLocals = false);
|
bool PreserveLocals = false);
|
||||||
|
|
||||||
} // namespace llvm
|
} // namespace llvm
|
||||||
|
@ -127,7 +127,7 @@ public:
|
|||||||
|
|
||||||
/// Find an unused register of the specified register class.
|
/// Find an unused register of the specified register class.
|
||||||
/// Return 0 if none is found.
|
/// Return 0 if none is found.
|
||||||
unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
|
unsigned FindUnusedReg(const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
/// Add a scavenging frame index.
|
/// Add a scavenging frame index.
|
||||||
void addScavengingFrameIndex(int FI) {
|
void addScavengingFrameIndex(int FI) {
|
||||||
@ -158,7 +158,7 @@ public:
|
|||||||
/// Returns the scavenged register.
|
/// Returns the scavenged register.
|
||||||
/// This is deprecated as it depends on the quality of the kill flags being
|
/// This is deprecated as it depends on the quality of the kill flags being
|
||||||
/// present; Use scavengeRegisterBackwards() instead!
|
/// present; Use scavengeRegisterBackwards() instead!
|
||||||
unsigned scavengeRegister(const TargetRegisterClass *RegClass,
|
unsigned scavengeRegister(const TargetRegisterClass *RC,
|
||||||
MachineBasicBlock::iterator I, int SPAdj);
|
MachineBasicBlock::iterator I, int SPAdj);
|
||||||
unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
|
unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
|
||||||
return scavengeRegister(RegClass, MBBI, SPAdj);
|
return scavengeRegister(RegClass, MBBI, SPAdj);
|
||||||
@ -218,7 +218,7 @@ private:
|
|||||||
/// Spill a register after position \p After and reload it before position
|
/// Spill a register after position \p After and reload it before position
|
||||||
/// \p UseMI.
|
/// \p UseMI.
|
||||||
ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
|
ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
|
||||||
MachineBasicBlock::iterator After,
|
MachineBasicBlock::iterator Before,
|
||||||
MachineBasicBlock::iterator &UseMI);
|
MachineBasicBlock::iterator &UseMI);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -32,7 +32,7 @@ namespace llvm {
|
|||||||
ResourcePriorityQueue *PQ;
|
ResourcePriorityQueue *PQ;
|
||||||
explicit resource_sort(ResourcePriorityQueue *pq) : PQ(pq) {}
|
explicit resource_sort(ResourcePriorityQueue *pq) : PQ(pq) {}
|
||||||
|
|
||||||
bool operator()(const SUnit* left, const SUnit* right) const;
|
bool operator()(const SUnit* LHS, const SUnit* RHS) const;
|
||||||
};
|
};
|
||||||
|
|
||||||
class ResourcePriorityQueue : public SchedulingPriorityQueue {
|
class ResourcePriorityQueue : public SchedulingPriorityQueue {
|
||||||
@ -121,7 +121,7 @@ namespace llvm {
|
|||||||
void remove(SUnit *SU) override;
|
void remove(SUnit *SU) override;
|
||||||
|
|
||||||
/// scheduledNode - Main resource tracking point.
|
/// scheduledNode - Main resource tracking point.
|
||||||
void scheduledNode(SUnit *Node) override;
|
void scheduledNode(SUnit *SU) override;
|
||||||
bool isResourceAvailable(SUnit *SU);
|
bool isResourceAvailable(SUnit *SU);
|
||||||
void reserveResources(SUnit *SU);
|
void reserveResources(SUnit *SU);
|
||||||
|
|
||||||
|
@ -462,8 +462,8 @@ class TargetRegisterInfo;
|
|||||||
void dump(const ScheduleDAG *G) const;
|
void dump(const ScheduleDAG *G) const;
|
||||||
void dumpAll(const ScheduleDAG *G) const;
|
void dumpAll(const ScheduleDAG *G) const;
|
||||||
raw_ostream &print(raw_ostream &O,
|
raw_ostream &print(raw_ostream &O,
|
||||||
const SUnit *N = nullptr,
|
const SUnit *Entry = nullptr,
|
||||||
const SUnit *X = nullptr) const;
|
const SUnit *Exit = nullptr) const;
|
||||||
raw_ostream &print(raw_ostream &O, const ScheduleDAG *G) const;
|
raw_ostream &print(raw_ostream &O, const ScheduleDAG *G) const;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
@ -106,7 +106,7 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer {
|
|||||||
Scoreboard RequiredScoreboard;
|
Scoreboard RequiredScoreboard;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
|
ScoreboardHazardRecognizer(const InstrItineraryData *II,
|
||||||
const ScheduleDAG *DAG,
|
const ScheduleDAG *DAG,
|
||||||
const char *ParentDebugType = "");
|
const char *ParentDebugType = "");
|
||||||
|
|
||||||
|
@ -382,7 +382,7 @@ public:
|
|||||||
/// Prepare this SelectionDAG to process code in the given MachineFunction.
|
/// Prepare this SelectionDAG to process code in the given MachineFunction.
|
||||||
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
|
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
|
||||||
Pass *PassPtr, const TargetLibraryInfo *LibraryInfo,
|
Pass *PassPtr, const TargetLibraryInfo *LibraryInfo,
|
||||||
DivergenceAnalysis * DA);
|
DivergenceAnalysis * Divergence);
|
||||||
|
|
||||||
void setFunctionLoweringInfo(FunctionLoweringInfo * FuncInfo) {
|
void setFunctionLoweringInfo(FunctionLoweringInfo * FuncInfo) {
|
||||||
FLI = FuncInfo;
|
FLI = FuncInfo;
|
||||||
@ -598,7 +598,7 @@ public:
|
|||||||
bool isTarget = false);
|
bool isTarget = false);
|
||||||
SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,
|
SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,
|
||||||
bool isTarget = false);
|
bool isTarget = false);
|
||||||
SDValue getConstantFP(const ConstantFP &CF, const SDLoc &DL, EVT VT,
|
SDValue getConstantFP(const ConstantFP &V, const SDLoc &DL, EVT VT,
|
||||||
bool isTarget = false);
|
bool isTarget = false);
|
||||||
SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {
|
SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {
|
||||||
return getConstantFP(Val, DL, VT, true);
|
return getConstantFP(Val, DL, VT, true);
|
||||||
@ -782,7 +782,7 @@ public:
|
|||||||
|
|
||||||
/// Return the expression required to zero extend the Op
|
/// Return the expression required to zero extend the Op
|
||||||
/// value assuming it was the smaller SrcTy value.
|
/// value assuming it was the smaller SrcTy value.
|
||||||
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy);
|
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
|
||||||
|
|
||||||
/// Return an operation which will any-extend the low lanes of the operand
|
/// Return an operation which will any-extend the low lanes of the operand
|
||||||
/// into the specified vector type. For example,
|
/// into the specified vector type. For example,
|
||||||
@ -879,12 +879,12 @@ public:
|
|||||||
ArrayRef<SDValue> Ops, const SDNodeFlags Flags = SDNodeFlags());
|
ArrayRef<SDValue> Ops, const SDNodeFlags Flags = SDNodeFlags());
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys,
|
||||||
ArrayRef<SDValue> Ops);
|
ArrayRef<SDValue> Ops);
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
|
||||||
ArrayRef<SDValue> Ops);
|
ArrayRef<SDValue> Ops);
|
||||||
|
|
||||||
// Specialize based on number of operands.
|
// Specialize based on number of operands.
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand,
|
||||||
const SDNodeFlags Flags = SDNodeFlags());
|
const SDNodeFlags Flags = SDNodeFlags());
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
|
||||||
SDValue N2, const SDNodeFlags Flags = SDNodeFlags());
|
SDValue N2, const SDNodeFlags Flags = SDNodeFlags());
|
||||||
@ -898,15 +898,15 @@ public:
|
|||||||
|
|
||||||
// Specialize again based on number of operands for nodes with a VTList
|
// Specialize again based on number of operands for nodes with a VTList
|
||||||
// rather than a single VT.
|
// rather than a single VT.
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs);
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList);
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N);
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N);
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
|
||||||
SDValue N2);
|
SDValue N2);
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
|
||||||
SDValue N2, SDValue N3);
|
SDValue N2, SDValue N3);
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
|
||||||
SDValue N2, SDValue N3, SDValue N4);
|
SDValue N2, SDValue N3, SDValue N4);
|
||||||
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
|
SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
|
||||||
SDValue N2, SDValue N3, SDValue N4, SDValue N5);
|
SDValue N2, SDValue N3, SDValue N4, SDValue N5);
|
||||||
|
|
||||||
/// Compute a TokenFactor to force all the incoming stack arguments to be
|
/// Compute a TokenFactor to force all the incoming stack arguments to be
|
||||||
@ -1085,12 +1085,12 @@ public:
|
|||||||
MachineMemOperand *MMO);
|
MachineMemOperand *MMO);
|
||||||
SDValue
|
SDValue
|
||||||
getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
|
getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
|
||||||
MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment = 0,
|
MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment = 0,
|
||||||
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
|
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
|
||||||
const AAMDNodes &AAInfo = AAMDNodes());
|
const AAMDNodes &AAInfo = AAMDNodes());
|
||||||
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
|
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
|
||||||
SDValue Ptr, EVT TVT, MachineMemOperand *MMO);
|
SDValue Ptr, EVT SVT, MachineMemOperand *MMO);
|
||||||
SDValue getIndexedStore(SDValue OrigStoe, const SDLoc &dl, SDValue Base,
|
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base,
|
||||||
SDValue Offset, ISD::MemIndexedMode AM);
|
SDValue Offset, ISD::MemIndexedMode AM);
|
||||||
|
|
||||||
/// Returns sum of the base pointer and offset.
|
/// Returns sum of the base pointer and offset.
|
||||||
@ -1163,24 +1163,24 @@ public:
|
|||||||
/// specified node to have the specified return type, Target opcode, and
|
/// specified node to have the specified return type, Target opcode, and
|
||||||
/// operands. Note that target opcodes are stored as
|
/// operands. Note that target opcodes are stored as
|
||||||
/// ~TargetOpcode in the node opcode field. The resultant node is returned.
|
/// ~TargetOpcode in the node opcode field. The resultant node is returned.
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT);
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1);
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
|
||||||
SDValue Op1, SDValue Op2);
|
SDValue Op1, SDValue Op2);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
|
||||||
SDValue Op1, SDValue Op2, SDValue Op3);
|
SDValue Op1, SDValue Op2, SDValue Op3);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
|
||||||
ArrayRef<SDValue> Ops);
|
ArrayRef<SDValue> Ops);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
|
||||||
EVT VT2, ArrayRef<SDValue> Ops);
|
EVT VT2, ArrayRef<SDValue> Ops);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
|
||||||
EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
|
EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
|
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
|
||||||
EVT VT2, SDValue Op1);
|
EVT VT2, SDValue Op1);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
|
||||||
EVT VT2, SDValue Op1, SDValue Op2);
|
EVT VT2, SDValue Op1, SDValue Op2);
|
||||||
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, SDVTList VTs,
|
SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, SDVTList VTs,
|
||||||
ArrayRef<SDValue> Ops);
|
ArrayRef<SDValue> Ops);
|
||||||
|
|
||||||
/// This *mutates* the specified node to have the specified
|
/// This *mutates* the specified node to have the specified
|
||||||
@ -1235,7 +1235,7 @@ public:
|
|||||||
SDValue Operand, SDValue Subreg);
|
SDValue Operand, SDValue Subreg);
|
||||||
|
|
||||||
/// Get the specified node if it's already available, or else return NULL.
|
/// Get the specified node if it's already available, or else return NULL.
|
||||||
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs, ArrayRef<SDValue> Ops,
|
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef<SDValue> Ops,
|
||||||
const SDNodeFlags Flags = SDNodeFlags());
|
const SDNodeFlags Flags = SDNodeFlags());
|
||||||
|
|
||||||
/// Creates a SDDbgValue node.
|
/// Creates a SDDbgValue node.
|
||||||
@ -1291,7 +1291,7 @@ public:
|
|||||||
/// to be given new uses. These new uses of From are left in place, and
|
/// to be given new uses. These new uses of From are left in place, and
|
||||||
/// not automatically transferred to To.
|
/// not automatically transferred to To.
|
||||||
///
|
///
|
||||||
void ReplaceAllUsesWith(SDValue From, SDValue Op);
|
void ReplaceAllUsesWith(SDValue From, SDValue To);
|
||||||
void ReplaceAllUsesWith(SDNode *From, SDNode *To);
|
void ReplaceAllUsesWith(SDNode *From, SDNode *To);
|
||||||
void ReplaceAllUsesWith(SDNode *From, const SDValue *To);
|
void ReplaceAllUsesWith(SDNode *From, const SDValue *To);
|
||||||
|
|
||||||
|
@ -292,14 +292,14 @@ private:
|
|||||||
|
|
||||||
// Calls to these functions are generated by tblgen.
|
// Calls to these functions are generated by tblgen.
|
||||||
void Select_INLINEASM(SDNode *N);
|
void Select_INLINEASM(SDNode *N);
|
||||||
void Select_READ_REGISTER(SDNode *N);
|
void Select_READ_REGISTER(SDNode *Op);
|
||||||
void Select_WRITE_REGISTER(SDNode *N);
|
void Select_WRITE_REGISTER(SDNode *Op);
|
||||||
void Select_UNDEF(SDNode *N);
|
void Select_UNDEF(SDNode *N);
|
||||||
void CannotYetSelect(SDNode *N);
|
void CannotYetSelect(SDNode *N);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
void DoInstructionSelection();
|
void DoInstructionSelection();
|
||||||
SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
|
SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
|
||||||
ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
|
ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
|
||||||
|
|
||||||
SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
|
SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
|
||||||
|
@ -1246,7 +1246,7 @@ protected:
|
|||||||
|
|
||||||
public:
|
public:
|
||||||
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
|
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
|
||||||
EVT MemoryVT, MachineMemOperand *MMO);
|
EVT memvt, MachineMemOperand *MMO);
|
||||||
|
|
||||||
bool readMem() const { return MMO->isLoad(); }
|
bool readMem() const { return MMO->isLoad(); }
|
||||||
bool writeMem() const { return MMO->isStore(); }
|
bool writeMem() const { return MMO->isStore(); }
|
||||||
@ -1594,10 +1594,10 @@ bool isOneConstant(SDValue V);
|
|||||||
bool isBitwiseNot(SDValue V);
|
bool isBitwiseNot(SDValue V);
|
||||||
|
|
||||||
/// Returns the SDNode if it is a constant splat BuildVector or constant int.
|
/// Returns the SDNode if it is a constant splat BuildVector or constant int.
|
||||||
ConstantSDNode *isConstOrConstSplat(SDValue V);
|
ConstantSDNode *isConstOrConstSplat(SDValue N);
|
||||||
|
|
||||||
/// Returns the SDNode if it is a constant splat BuildVector or constant float.
|
/// Returns the SDNode if it is a constant splat BuildVector or constant float.
|
||||||
ConstantFPSDNode *isConstOrConstSplatFP(SDValue V);
|
ConstantFPSDNode *isConstOrConstSplatFP(SDValue N);
|
||||||
|
|
||||||
class GlobalAddressSDNode : public SDNode {
|
class GlobalAddressSDNode : public SDNode {
|
||||||
friend class SelectionDAG;
|
friend class SelectionDAG;
|
||||||
@ -1608,7 +1608,7 @@ class GlobalAddressSDNode : public SDNode {
|
|||||||
|
|
||||||
GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
|
GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
|
||||||
const GlobalValue *GA, EVT VT, int64_t o,
|
const GlobalValue *GA, EVT VT, int64_t o,
|
||||||
unsigned char TargetFlags);
|
unsigned char TF);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
const GlobalValue *getGlobal() const { return TheGlobal; }
|
const GlobalValue *getGlobal() const { return TheGlobal; }
|
||||||
|
@ -81,7 +81,7 @@ public:
|
|||||||
|
|
||||||
/// Given a machine instruction descriptor, returns the register
|
/// Given a machine instruction descriptor, returns the register
|
||||||
/// class constraint for OpNum, or NULL.
|
/// class constraint for OpNum, or NULL.
|
||||||
const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
|
const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
|
||||||
const TargetRegisterInfo *TRI,
|
const TargetRegisterInfo *TRI,
|
||||||
const MachineFunction &MF) const;
|
const MachineFunction &MF) const;
|
||||||
|
|
||||||
@ -909,7 +909,7 @@ public:
|
|||||||
/// The new instruction is inserted before MI, and the client is responsible
|
/// The new instruction is inserted before MI, and the client is responsible
|
||||||
/// for removing the old instruction.
|
/// for removing the old instruction.
|
||||||
MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
|
MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
|
||||||
int FrameIndex,
|
int FI,
|
||||||
LiveIntervals *LIS = nullptr) const;
|
LiveIntervals *LIS = nullptr) const;
|
||||||
|
|
||||||
/// Same as the previous version except it allows folding of any load and
|
/// Same as the previous version except it allows folding of any load and
|
||||||
@ -967,7 +967,7 @@ public:
|
|||||||
MachineInstr &Root, MachineCombinerPattern Pattern,
|
MachineInstr &Root, MachineCombinerPattern Pattern,
|
||||||
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
||||||
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
||||||
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
|
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
|
||||||
|
|
||||||
/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
|
/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
|
||||||
/// reduce critical path length.
|
/// reduce critical path length.
|
||||||
|
@ -2820,7 +2820,7 @@ public:
|
|||||||
/// results of this function, because simply replacing replacing TLO.Old
|
/// results of this function, because simply replacing replacing TLO.Old
|
||||||
/// with TLO.New will be incorrect when this parameter is true and TLO.Old
|
/// with TLO.New will be incorrect when this parameter is true and TLO.Old
|
||||||
/// has multiple uses.
|
/// has multiple uses.
|
||||||
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
|
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
|
||||||
APInt &KnownUndef, APInt &KnownZero,
|
APInt &KnownUndef, APInt &KnownZero,
|
||||||
TargetLoweringOpt &TLO, unsigned Depth = 0,
|
TargetLoweringOpt &TLO, unsigned Depth = 0,
|
||||||
bool AssumeSingleUse = false) const;
|
bool AssumeSingleUse = false) const;
|
||||||
@ -2903,7 +2903,7 @@ public:
|
|||||||
bool isConstFalseVal(const SDNode *N) const;
|
bool isConstFalseVal(const SDNode *N) const;
|
||||||
|
|
||||||
/// Return if \p N is a True value when extended to \p VT.
|
/// Return if \p N is a True value when extended to \p VT.
|
||||||
bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
|
bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
|
||||||
|
|
||||||
/// Try to simplify a setcc built with the specified operands and cc. If it is
|
/// Try to simplify a setcc built with the specified operands and cc. If it is
|
||||||
/// unable to simplify it, return a null SDValue.
|
/// unable to simplify it, return a null SDValue.
|
||||||
@ -3624,7 +3624,7 @@ public:
|
|||||||
/// bounds the returned pointer is unspecified, but will be within the vector
|
/// bounds the returned pointer is unspecified, but will be within the vector
|
||||||
/// bounds.
|
/// bounds.
|
||||||
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
|
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
|
||||||
SDValue Idx) const;
|
SDValue Index) const;
|
||||||
|
|
||||||
//===--------------------------------------------------------------------===//
|
//===--------------------------------------------------------------------===//
|
||||||
// Instruction Emitting Hooks
|
// Instruction Emitting Hooks
|
||||||
|
@ -47,7 +47,7 @@ public:
|
|||||||
/// Emit Obj-C garbage collection and linker options.
|
/// Emit Obj-C garbage collection and linker options.
|
||||||
void emitModuleMetadata(MCStreamer &Streamer, Module &M) const override;
|
void emitModuleMetadata(MCStreamer &Streamer, Module &M) const override;
|
||||||
|
|
||||||
void emitPersonalityValue(MCStreamer &Streamer, const DataLayout &TM,
|
void emitPersonalityValue(MCStreamer &Streamer, const DataLayout &DL,
|
||||||
const MCSymbol *Sym) const override;
|
const MCSymbol *Sym) const override;
|
||||||
|
|
||||||
/// Given a constant with the SectionKind, return a section that it should be
|
/// Given a constant with the SectionKind, return a section that it should be
|
||||||
|
@ -238,12 +238,12 @@ private:
|
|||||||
|
|
||||||
protected:
|
protected:
|
||||||
TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
|
TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
|
||||||
regclass_iterator RegClassBegin,
|
regclass_iterator RCB,
|
||||||
regclass_iterator RegClassEnd,
|
regclass_iterator RCE,
|
||||||
const char *const *SRINames,
|
const char *const *SRINames,
|
||||||
const LaneBitmask *SRILaneMasks,
|
const LaneBitmask *SRILaneMasks,
|
||||||
LaneBitmask CoveringLanes,
|
LaneBitmask CoveringLanes,
|
||||||
const RegClassInfo *const RSI,
|
const RegClassInfo *const RCIs,
|
||||||
unsigned Mode = 0);
|
unsigned Mode = 0);
|
||||||
virtual ~TargetRegisterInfo();
|
virtual ~TargetRegisterInfo();
|
||||||
|
|
||||||
@ -1167,7 +1167,7 @@ struct VirtReg2IndexFunctor {
|
|||||||
///
|
///
|
||||||
/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
|
/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
|
||||||
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
|
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
|
||||||
unsigned SubRegIdx = 0,
|
unsigned SubIdx = 0,
|
||||||
const MachineRegisterInfo *MRI = nullptr);
|
const MachineRegisterInfo *MRI = nullptr);
|
||||||
|
|
||||||
/// Create Printable object to print register units on a \ref raw_ostream.
|
/// Create Printable object to print register units on a \ref raw_ostream.
|
||||||
|
@ -185,14 +185,14 @@ public:
|
|||||||
/// if converter after moving it to TargetSchedModel).
|
/// if converter after moving it to TargetSchedModel).
|
||||||
unsigned computeInstrLatency(const MachineInstr *MI,
|
unsigned computeInstrLatency(const MachineInstr *MI,
|
||||||
bool UseDefaultDefLatency = true) const;
|
bool UseDefaultDefLatency = true) const;
|
||||||
unsigned computeInstrLatency(const MCInst &MI) const;
|
unsigned computeInstrLatency(const MCInst &Inst) const;
|
||||||
unsigned computeInstrLatency(unsigned Opcode) const;
|
unsigned computeInstrLatency(unsigned Opcode) const;
|
||||||
|
|
||||||
|
|
||||||
/// Output dependency latency of a pair of defs of the same register.
|
/// Output dependency latency of a pair of defs of the same register.
|
||||||
///
|
///
|
||||||
/// This is typically one cycle.
|
/// This is typically one cycle.
|
||||||
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
|
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
|
||||||
const MachineInstr *DepMI) const;
|
const MachineInstr *DepMI) const;
|
||||||
|
|
||||||
/// Compute the reciprocal throughput of the given instruction.
|
/// Compute the reciprocal throughput of the given instruction.
|
||||||
|
@ -172,7 +172,7 @@ class TargetInstrInfo;
|
|||||||
|
|
||||||
/// create a mapping for the specified virtual register to
|
/// create a mapping for the specified virtual register to
|
||||||
/// the specified stack slot
|
/// the specified stack slot
|
||||||
void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
|
void assignVirt2StackSlot(unsigned virtReg, int SS);
|
||||||
|
|
||||||
void print(raw_ostream &OS, const Module* M = nullptr) const override;
|
void print(raw_ostream &OS, const Module* M = nullptr) const override;
|
||||||
void dump() const;
|
void dump() const;
|
||||||
|
@ -73,7 +73,7 @@ struct WasmEHFuncInfo {
|
|||||||
};
|
};
|
||||||
|
|
||||||
// Analyze the IR in the given function to build WasmEHFuncInfo.
|
// Analyze the IR in the given function to build WasmEHFuncInfo.
|
||||||
void calculateWasmEHInfo(const Function *F, WasmEHFuncInfo &FuncInfo);
|
void calculateWasmEHInfo(const Function *F, WasmEHFuncInfo &EHInfo);
|
||||||
|
|
||||||
} // namespace llvm
|
} // namespace llvm
|
||||||
|
|
||||||
|
@ -305,7 +305,7 @@ public:
|
|||||||
class LLVMTargetMachine : public TargetMachine {
|
class LLVMTargetMachine : public TargetMachine {
|
||||||
protected: // Can only create subclasses.
|
protected: // Can only create subclasses.
|
||||||
LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
|
LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
|
||||||
const Triple &TargetTriple, StringRef CPU, StringRef FS,
|
const Triple &TT, StringRef CPU, StringRef FS,
|
||||||
const TargetOptions &Options, Reloc::Model RM,
|
const TargetOptions &Options, Reloc::Model RM,
|
||||||
CodeModel::Model CM, CodeGenOpt::Level OL);
|
CodeModel::Model CM, CodeGenOpt::Level OL);
|
||||||
|
|
||||||
@ -336,7 +336,7 @@ public:
|
|||||||
/// fills the MCContext Ctx pointer which can be used to build custom
|
/// fills the MCContext Ctx pointer which can be used to build custom
|
||||||
/// MCStreamer.
|
/// MCStreamer.
|
||||||
bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
|
bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
|
||||||
raw_pwrite_stream &OS,
|
raw_pwrite_stream &Out,
|
||||||
bool DisableVerify = true) override;
|
bool DisableVerify = true) override;
|
||||||
|
|
||||||
/// Returns true if the target is expected to pass all machine verifier
|
/// Returns true if the target is expected to pass all machine verifier
|
||||||
|
@ -233,7 +233,7 @@ class Dwarf5AccelTableWriter : public AccelTableWriter {
|
|||||||
void emitBuckets() const;
|
void emitBuckets() const;
|
||||||
void emitStringOffsets() const;
|
void emitStringOffsets() const;
|
||||||
void emitAbbrevs() const;
|
void emitAbbrevs() const;
|
||||||
void emitEntry(const DataT &Data) const;
|
void emitEntry(const DataT &Entry) const;
|
||||||
void emitData() const;
|
void emitData() const;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
@ -225,7 +225,7 @@ class LLVM_LIBRARY_VISIBILITY CodeViewDebug : public DebugHandlerBase {
|
|||||||
using FileToFilepathMapTy = std::map<const DIFile *, std::string>;
|
using FileToFilepathMapTy = std::map<const DIFile *, std::string>;
|
||||||
FileToFilepathMapTy FileToFilepathMap;
|
FileToFilepathMapTy FileToFilepathMap;
|
||||||
|
|
||||||
StringRef getFullFilepath(const DIFile *S);
|
StringRef getFullFilepath(const DIFile *File);
|
||||||
|
|
||||||
unsigned maybeRecordFile(const DIFile *F);
|
unsigned maybeRecordFile(const DIFile *F);
|
||||||
|
|
||||||
@ -386,7 +386,7 @@ protected:
|
|||||||
void endFunctionImpl(const MachineFunction *) override;
|
void endFunctionImpl(const MachineFunction *) override;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
CodeViewDebug(AsmPrinter *Asm);
|
CodeViewDebug(AsmPrinter *AP);
|
||||||
|
|
||||||
void setSymbolSize(const MCSymbol *, uint64_t) override {}
|
void setSymbolSize(const MCSymbol *, uint64_t) override {}
|
||||||
|
|
||||||
|
@ -44,7 +44,7 @@ public:
|
|||||||
// Helper routines to process parts of a DIE.
|
// Helper routines to process parts of a DIE.
|
||||||
private:
|
private:
|
||||||
/// Adds the parent context of \param Die to the hash.
|
/// Adds the parent context of \param Die to the hash.
|
||||||
void addParentContext(const DIE &Die);
|
void addParentContext(const DIE &Parent);
|
||||||
|
|
||||||
/// Adds the attributes of \param Die to the hash.
|
/// Adds the attributes of \param Die to the hash.
|
||||||
void addAttributes(const DIE &Die);
|
void addAttributes(const DIE &Die);
|
||||||
|
@ -217,7 +217,7 @@ public:
|
|||||||
DbgVariable *getExistingAbstractVariable(InlinedVariable IV,
|
DbgVariable *getExistingAbstractVariable(InlinedVariable IV,
|
||||||
const DILocalVariable *&Cleansed);
|
const DILocalVariable *&Cleansed);
|
||||||
DbgVariable *getExistingAbstractVariable(InlinedVariable IV);
|
DbgVariable *getExistingAbstractVariable(InlinedVariable IV);
|
||||||
void createAbstractVariable(const DILocalVariable *DV, LexicalScope *Scope);
|
void createAbstractVariable(const DILocalVariable *Var, LexicalScope *Scope);
|
||||||
|
|
||||||
/// Set the skeleton unit associated with this unit.
|
/// Set the skeleton unit associated with this unit.
|
||||||
void setSkeleton(DwarfCompileUnit &Skel) { Skeleton = &Skel; }
|
void setSkeleton(DwarfCompileUnit &Skel) { Skeleton = &Skel; }
|
||||||
|
@ -331,9 +331,9 @@ class DwarfDebug : public DebugHandlerBase {
|
|||||||
|
|
||||||
using InlinedVariable = DbgValueHistoryMap::InlinedVariable;
|
using InlinedVariable = DbgValueHistoryMap::InlinedVariable;
|
||||||
|
|
||||||
void ensureAbstractVariableIsCreated(DwarfCompileUnit &CU, InlinedVariable Var,
|
void ensureAbstractVariableIsCreated(DwarfCompileUnit &CU, InlinedVariable IV,
|
||||||
const MDNode *Scope);
|
const MDNode *Scope);
|
||||||
void ensureAbstractVariableIsCreatedIfScoped(DwarfCompileUnit &CU, InlinedVariable Var,
|
void ensureAbstractVariableIsCreatedIfScoped(DwarfCompileUnit &CU, InlinedVariable IV,
|
||||||
const MDNode *Scope);
|
const MDNode *Scope);
|
||||||
|
|
||||||
DbgVariable *createConcreteVariable(DwarfCompileUnit &TheCU,
|
DbgVariable *createConcreteVariable(DwarfCompileUnit &TheCU,
|
||||||
|
@ -98,7 +98,7 @@ protected:
|
|||||||
/// corresponds to the MDNode mapped with the subprogram DIE.
|
/// corresponds to the MDNode mapped with the subprogram DIE.
|
||||||
DenseMap<DIE *, const DINode *> ContainingTypeMap;
|
DenseMap<DIE *, const DINode *> ContainingTypeMap;
|
||||||
|
|
||||||
DwarfUnit(dwarf::Tag, const DICompileUnit *CU, AsmPrinter *A, DwarfDebug *DW,
|
DwarfUnit(dwarf::Tag, const DICompileUnit *Node, AsmPrinter *A, DwarfDebug *DW,
|
||||||
DwarfFile *DWU);
|
DwarfFile *DWU);
|
||||||
|
|
||||||
bool applySubprogramDefinitionAttributes(const DISubprogram *SP, DIE &SPDie);
|
bool applySubprogramDefinitionAttributes(const DISubprogram *SP, DIE &SPDie);
|
||||||
@ -187,7 +187,7 @@ public:
|
|||||||
|
|
||||||
/// Add a dwarf op address data and value using the form given and an
|
/// Add a dwarf op address data and value using the form given and an
|
||||||
/// op of either DW_FORM_addr or DW_FORM_GNU_addr_index.
|
/// op of either DW_FORM_addr or DW_FORM_GNU_addr_index.
|
||||||
void addOpAddress(DIELoc &Die, const MCSymbol *Label);
|
void addOpAddress(DIELoc &Die, const MCSymbol *Sym);
|
||||||
|
|
||||||
/// Add a label delta attribute data and value.
|
/// Add a label delta attribute data and value.
|
||||||
void addLabelDelta(DIE &Die, dwarf::Attribute Attribute, const MCSymbol *Hi,
|
void addLabelDelta(DIE &Die, dwarf::Attribute Attribute, const MCSymbol *Hi,
|
||||||
@ -203,7 +203,7 @@ public:
|
|||||||
void addDIETypeSignature(DIE &Die, uint64_t Signature);
|
void addDIETypeSignature(DIE &Die, uint64_t Signature);
|
||||||
|
|
||||||
/// Add block data.
|
/// Add block data.
|
||||||
void addBlock(DIE &Die, dwarf::Attribute Attribute, DIELoc *Block);
|
void addBlock(DIE &Die, dwarf::Attribute Attribute, DIELoc *Loc);
|
||||||
|
|
||||||
/// Add block data.
|
/// Add block data.
|
||||||
void addBlock(DIE &Die, dwarf::Attribute Attribute, DIEBlock *Block);
|
void addBlock(DIE &Die, dwarf::Attribute Attribute, DIEBlock *Block);
|
||||||
@ -260,7 +260,7 @@ public:
|
|||||||
bool SkipSPAttributes = false);
|
bool SkipSPAttributes = false);
|
||||||
|
|
||||||
/// Find existing DIE or create new DIE for the given type.
|
/// Find existing DIE or create new DIE for the given type.
|
||||||
DIE *getOrCreateTypeDIE(const MDNode *N);
|
DIE *getOrCreateTypeDIE(const MDNode *TyNode);
|
||||||
|
|
||||||
/// Get context owner's DIE.
|
/// Get context owner's DIE.
|
||||||
DIE *getOrCreateContextDIE(const DIScope *Context);
|
DIE *getOrCreateContextDIE(const DIScope *Context);
|
||||||
@ -342,7 +342,7 @@ protected:
|
|||||||
private:
|
private:
|
||||||
void constructTypeDIE(DIE &Buffer, const DIBasicType *BTy);
|
void constructTypeDIE(DIE &Buffer, const DIBasicType *BTy);
|
||||||
void constructTypeDIE(DIE &Buffer, const DIDerivedType *DTy);
|
void constructTypeDIE(DIE &Buffer, const DIDerivedType *DTy);
|
||||||
void constructTypeDIE(DIE &Buffer, const DISubroutineType *DTy);
|
void constructTypeDIE(DIE &Buffer, const DISubroutineType *CTy);
|
||||||
void constructSubrangeDIE(DIE &Buffer, const DISubrange *SR, DIE *IndexTy);
|
void constructSubrangeDIE(DIE &Buffer, const DISubrange *SR, DIE *IndexTy);
|
||||||
void constructArrayTypeDIE(DIE &Buffer, const DICompositeType *CTy);
|
void constructArrayTypeDIE(DIE &Buffer, const DICompositeType *CTy);
|
||||||
void constructEnumTypeDIE(DIE &Buffer, const DICompositeType *CTy);
|
void constructEnumTypeDIE(DIE &Buffer, const DICompositeType *CTy);
|
||||||
|
@ -72,7 +72,7 @@ protected:
|
|||||||
|
|
||||||
/// Compute the actions table and gather the first action index for each
|
/// Compute the actions table and gather the first action index for each
|
||||||
/// landing pad site.
|
/// landing pad site.
|
||||||
void computeActionsTable(const SmallVectorImpl<const LandingPadInfo *> &LPs,
|
void computeActionsTable(const SmallVectorImpl<const LandingPadInfo *> &LandingPads,
|
||||||
SmallVectorImpl<ActionEntry> &Actions,
|
SmallVectorImpl<ActionEntry> &Actions,
|
||||||
SmallVectorImpl<unsigned> &FirstActions);
|
SmallVectorImpl<unsigned> &FirstActions);
|
||||||
|
|
||||||
@ -86,7 +86,7 @@ protected:
|
|||||||
/// no entry and must not be contained in the try-range of any entry - they
|
/// no entry and must not be contained in the try-range of any entry - they
|
||||||
/// form gaps in the table. Entries must be ordered by try-range address.
|
/// form gaps in the table. Entries must be ordered by try-range address.
|
||||||
void computeCallSiteTable(SmallVectorImpl<CallSiteEntry> &CallSites,
|
void computeCallSiteTable(SmallVectorImpl<CallSiteEntry> &CallSites,
|
||||||
const SmallVectorImpl<const LandingPadInfo *> &LPs,
|
const SmallVectorImpl<const LandingPadInfo *> &LandingPads,
|
||||||
const SmallVectorImpl<unsigned> &FirstActions);
|
const SmallVectorImpl<unsigned> &FirstActions);
|
||||||
|
|
||||||
/// Emit landing pads and actions.
|
/// Emit landing pads and actions.
|
||||||
|
@ -98,8 +98,8 @@ namespace {
|
|||||||
CreateCmpXchgInstFun CreateCmpXchg);
|
CreateCmpXchgInstFun CreateCmpXchg);
|
||||||
|
|
||||||
bool expandAtomicCmpXchg(AtomicCmpXchgInst *CI);
|
bool expandAtomicCmpXchg(AtomicCmpXchgInst *CI);
|
||||||
bool isIdempotentRMW(AtomicRMWInst *AI);
|
bool isIdempotentRMW(AtomicRMWInst *RMWI);
|
||||||
bool simplifyIdempotentRMW(AtomicRMWInst *AI);
|
bool simplifyIdempotentRMW(AtomicRMWInst *RMWI);
|
||||||
|
|
||||||
bool expandAtomicOpToLibcall(Instruction *I, unsigned Size, unsigned Align,
|
bool expandAtomicOpToLibcall(Instruction *I, unsigned Size, unsigned Align,
|
||||||
Value *PointerOperand, Value *ValueOperand,
|
Value *PointerOperand, Value *ValueOperand,
|
||||||
|
@ -38,11 +38,11 @@ class TargetRegisterInfo;
|
|||||||
|
|
||||||
explicit BranchFolder(bool defaultEnableTailMerge,
|
explicit BranchFolder(bool defaultEnableTailMerge,
|
||||||
bool CommonHoist,
|
bool CommonHoist,
|
||||||
MBFIWrapper &MBFI,
|
MBFIWrapper &FreqInfo,
|
||||||
const MachineBranchProbabilityInfo &MBPI,
|
const MachineBranchProbabilityInfo &ProbInfo,
|
||||||
// Min tail length to merge. Defaults to commandline
|
// Min tail length to merge. Defaults to commandline
|
||||||
// flag. Ignored for optsize.
|
// flag. Ignored for optsize.
|
||||||
unsigned MinCommonTailLength = 0);
|
unsigned MinTailLength = 0);
|
||||||
|
|
||||||
/// Perhaps branch folding, tail merging and other CFG optimizations on the
|
/// Perhaps branch folding, tail merging and other CFG optimizations on the
|
||||||
/// given function. Block placement changes the layout and may create new
|
/// given function. Block placement changes the layout and may create new
|
||||||
|
@ -96,7 +96,7 @@ class BranchRelaxation : public MachineFunctionPass {
|
|||||||
|
|
||||||
MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI,
|
MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI,
|
||||||
MachineBasicBlock *DestBB);
|
MachineBasicBlock *DestBB);
|
||||||
void adjustBlockOffsets(MachineBasicBlock &MBB);
|
void adjustBlockOffsets(MachineBasicBlock &Start);
|
||||||
bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const;
|
bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const;
|
||||||
|
|
||||||
bool fixupConditionalBranch(MachineInstr &MI);
|
bool fixupConditionalBranch(MachineInstr &MI);
|
||||||
|
@ -321,16 +321,16 @@ class TypePromotionTransaction;
|
|||||||
bool isPreheader);
|
bool isPreheader);
|
||||||
bool optimizeBlock(BasicBlock &BB, bool &ModifiedDT);
|
bool optimizeBlock(BasicBlock &BB, bool &ModifiedDT);
|
||||||
bool optimizeInst(Instruction *I, bool &ModifiedDT);
|
bool optimizeInst(Instruction *I, bool &ModifiedDT);
|
||||||
bool optimizeMemoryInst(Instruction *I, Value *Addr,
|
bool optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
|
||||||
Type *AccessTy, unsigned AS);
|
Type *AccessTy, unsigned AddrSpace);
|
||||||
bool optimizeInlineAsmInst(CallInst *CS);
|
bool optimizeInlineAsmInst(CallInst *CS);
|
||||||
bool optimizeCallInst(CallInst *CI, bool &ModifiedDT);
|
bool optimizeCallInst(CallInst *CI, bool &ModifiedDT);
|
||||||
bool optimizeExt(Instruction *&I);
|
bool optimizeExt(Instruction *&I);
|
||||||
bool optimizeExtUses(Instruction *I);
|
bool optimizeExtUses(Instruction *I);
|
||||||
bool optimizeLoadExt(LoadInst *I);
|
bool optimizeLoadExt(LoadInst *Load);
|
||||||
bool optimizeSelectInst(SelectInst *SI);
|
bool optimizeSelectInst(SelectInst *SI);
|
||||||
bool optimizeShuffleVectorInst(ShuffleVectorInst *SI);
|
bool optimizeShuffleVectorInst(ShuffleVectorInst *SVI);
|
||||||
bool optimizeSwitchInst(SwitchInst *CI);
|
bool optimizeSwitchInst(SwitchInst *SI);
|
||||||
bool optimizeExtractElementInst(Instruction *Inst);
|
bool optimizeExtractElementInst(Instruction *Inst);
|
||||||
bool dupRetToEnableTailCallOpts(BasicBlock *BB);
|
bool dupRetToEnableTailCallOpts(BasicBlock *BB);
|
||||||
bool placeDbgValues(Function &F);
|
bool placeDbgValues(Function &F);
|
||||||
@ -2612,8 +2612,8 @@ public:
|
|||||||
|
|
||||||
private:
|
private:
|
||||||
bool matchScaledValue(Value *ScaleReg, int64_t Scale, unsigned Depth);
|
bool matchScaledValue(Value *ScaleReg, int64_t Scale, unsigned Depth);
|
||||||
bool matchAddr(Value *V, unsigned Depth);
|
bool matchAddr(Value *Addr, unsigned Depth);
|
||||||
bool matchOperationAddr(User *Operation, unsigned Opcode, unsigned Depth,
|
bool matchOperationAddr(User *AddrInst, unsigned Opcode, unsigned Depth,
|
||||||
bool *MovedAway = nullptr);
|
bool *MovedAway = nullptr);
|
||||||
bool isProfitableToFoldIntoAddressingMode(Instruction *I,
|
bool isProfitableToFoldIntoAddressingMode(Instruction *I,
|
||||||
ExtAddrMode &AMBefore,
|
ExtAddrMode &AMBefore,
|
||||||
|
@ -102,7 +102,7 @@ class MemCmpExpansion {
|
|||||||
MemCmpExpansion(CallInst *CI, uint64_t Size,
|
MemCmpExpansion(CallInst *CI, uint64_t Size,
|
||||||
const TargetTransformInfo::MemCmpExpansionOptions &Options,
|
const TargetTransformInfo::MemCmpExpansionOptions &Options,
|
||||||
unsigned MaxNumLoads, const bool IsUsedForZeroCmp,
|
unsigned MaxNumLoads, const bool IsUsedForZeroCmp,
|
||||||
unsigned NumLoadsPerBlockForZeroCmp, const DataLayout &DL);
|
unsigned MaxLoadsPerBlockForZeroCmp, const DataLayout &TheDataLayout);
|
||||||
|
|
||||||
unsigned getNumBlocks();
|
unsigned getNumBlocks();
|
||||||
uint64_t getNumLoads() const { return LoadSequence.size(); }
|
uint64_t getNumLoads() const { return LoadSequence.size(); }
|
||||||
|
@ -38,7 +38,7 @@ namespace {
|
|||||||
/// directed by the GCStrategy. It also performs automatic root initialization
|
/// directed by the GCStrategy. It also performs automatic root initialization
|
||||||
/// and custom intrinsic lowering.
|
/// and custom intrinsic lowering.
|
||||||
class LowerIntrinsics : public FunctionPass {
|
class LowerIntrinsics : public FunctionPass {
|
||||||
bool PerformDefaultLowering(Function &F, GCStrategy &Coll);
|
bool PerformDefaultLowering(Function &F, GCStrategy &S);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
static char ID;
|
static char ID;
|
||||||
@ -61,7 +61,7 @@ class GCMachineCodeAnalysis : public MachineFunctionPass {
|
|||||||
const TargetInstrInfo *TII;
|
const TargetInstrInfo *TII;
|
||||||
|
|
||||||
void FindSafePoints(MachineFunction &MF);
|
void FindSafePoints(MachineFunction &MF);
|
||||||
void VisitCallPoint(MachineBasicBlock::iterator MI);
|
void VisitCallPoint(MachineBasicBlock::iterator CI);
|
||||||
MCSymbol *InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
MCSymbol *InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
const DebugLoc &DL) const;
|
const DebugLoc &DL) const;
|
||||||
|
|
||||||
|
@ -252,7 +252,7 @@ namespace {
|
|||||||
BBInfo &TrueBBI, BBInfo &FalseBBI) const;
|
BBInfo &TrueBBI, BBInfo &FalseBBI) const;
|
||||||
void AnalyzeBlock(MachineBasicBlock &MBB,
|
void AnalyzeBlock(MachineBasicBlock &MBB,
|
||||||
std::vector<std::unique_ptr<IfcvtToken>> &Tokens);
|
std::vector<std::unique_ptr<IfcvtToken>> &Tokens);
|
||||||
bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Cond,
|
bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Pred,
|
||||||
bool isTriangle = false, bool RevBranch = false,
|
bool isTriangle = false, bool RevBranch = false,
|
||||||
bool hasCommonTail = false);
|
bool hasCommonTail = false);
|
||||||
void AnalyzeBlocks(MachineFunction &MF,
|
void AnalyzeBlocks(MachineFunction &MF,
|
||||||
|
@ -115,7 +115,7 @@ class ImplicitNullChecks : public MachineFunctionPass {
|
|||||||
/// \c canHandle should return true for all instructions in \p
|
/// \c canHandle should return true for all instructions in \p
|
||||||
/// Insts.
|
/// Insts.
|
||||||
DependenceResult computeDependence(const MachineInstr *MI,
|
DependenceResult computeDependence(const MachineInstr *MI,
|
||||||
ArrayRef<MachineInstr *> Insts);
|
ArrayRef<MachineInstr *> Block);
|
||||||
|
|
||||||
/// Represents one null check that can be made implicit.
|
/// Represents one null check that can be made implicit.
|
||||||
class NullCheck {
|
class NullCheck {
|
||||||
|
@ -307,7 +307,7 @@ public:
|
|||||||
|
|
||||||
/// splitRegister - Replace OldReg ranges with NewRegs ranges where NewRegs is
|
/// splitRegister - Replace OldReg ranges with NewRegs ranges where NewRegs is
|
||||||
/// live. Returns true if any changes were made.
|
/// live. Returns true if any changes were made.
|
||||||
bool splitRegister(unsigned OldLocNo, ArrayRef<unsigned> NewRegs,
|
bool splitRegister(unsigned OldReg, ArrayRef<unsigned> NewRegs,
|
||||||
LiveIntervals &LIS);
|
LiveIntervals &LIS);
|
||||||
|
|
||||||
/// rewriteLocations - Rewrite virtual register locations according to the
|
/// rewriteLocations - Rewrite virtual register locations according to the
|
||||||
|
@ -147,7 +147,7 @@ class LiveRangeCalc {
|
|||||||
///
|
///
|
||||||
/// PhysReg, when set, is used to verify live-in lists on basic blocks.
|
/// PhysReg, when set, is used to verify live-in lists on basic blocks.
|
||||||
bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
|
bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
|
||||||
SlotIndex Kill, unsigned PhysReg,
|
SlotIndex Use, unsigned PhysReg,
|
||||||
ArrayRef<SlotIndex> Undefs);
|
ArrayRef<SlotIndex> Undefs);
|
||||||
|
|
||||||
/// updateSSA - Compute the values that will be live in to all requested
|
/// updateSSA - Compute the values that will be live in to all requested
|
||||||
|
@ -203,7 +203,7 @@ public:
|
|||||||
bool parseRegisterOperand(MachineOperand &Dest,
|
bool parseRegisterOperand(MachineOperand &Dest,
|
||||||
Optional<unsigned> &TiedDefIdx, bool IsDef = false);
|
Optional<unsigned> &TiedDefIdx, bool IsDef = false);
|
||||||
bool parseImmediateOperand(MachineOperand &Dest);
|
bool parseImmediateOperand(MachineOperand &Dest);
|
||||||
bool parseIRConstant(StringRef::iterator Loc, StringRef Source,
|
bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue,
|
||||||
const Constant *&C);
|
const Constant *&C);
|
||||||
bool parseIRConstant(StringRef::iterator Loc, const Constant *&C);
|
bool parseIRConstant(StringRef::iterator Loc, const Constant *&C);
|
||||||
bool parseLowLevelType(StringRef::iterator Loc, LLT &Ty);
|
bool parseLowLevelType(StringRef::iterator Loc, LLT &Ty);
|
||||||
@ -222,7 +222,7 @@ public:
|
|||||||
bool parseJumpTableIndexOperand(MachineOperand &Dest);
|
bool parseJumpTableIndexOperand(MachineOperand &Dest);
|
||||||
bool parseExternalSymbolOperand(MachineOperand &Dest);
|
bool parseExternalSymbolOperand(MachineOperand &Dest);
|
||||||
bool parseMDNode(MDNode *&Node);
|
bool parseMDNode(MDNode *&Node);
|
||||||
bool parseDIExpression(MDNode *&Node);
|
bool parseDIExpression(MDNode *&Expr);
|
||||||
bool parseMetadataOperand(MachineOperand &Dest);
|
bool parseMetadataOperand(MachineOperand &Dest);
|
||||||
bool parseCFIOffset(int &Offset);
|
bool parseCFIOffset(int &Offset);
|
||||||
bool parseCFIRegister(unsigned &Reg);
|
bool parseCFIRegister(unsigned &Reg);
|
||||||
|
@ -67,7 +67,7 @@ struct PerFunctionMIParsingState {
|
|||||||
const Name2RegClassMap &Names2RegClasses,
|
const Name2RegClassMap &Names2RegClasses,
|
||||||
const Name2RegBankMap &Names2RegBanks);
|
const Name2RegBankMap &Names2RegBanks);
|
||||||
|
|
||||||
VRegInfo &getVRegInfo(unsigned VReg);
|
VRegInfo &getVRegInfo(unsigned Num);
|
||||||
VRegInfo &getVRegInfoNamed(StringRef RegName);
|
VRegInfo &getVRegInfoNamed(StringRef RegName);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -425,7 +425,7 @@ class MachineBlockPlacement : public MachineFunctionPass {
|
|||||||
MachineBasicBlock *BB, MachineBasicBlock *LPred,
|
MachineBasicBlock *BB, MachineBasicBlock *LPred,
|
||||||
BlockChain &Chain, BlockFilterSet *BlockFilter,
|
BlockChain &Chain, BlockFilterSet *BlockFilter,
|
||||||
MachineFunction::iterator &PrevUnplacedBlockIt,
|
MachineFunction::iterator &PrevUnplacedBlockIt,
|
||||||
bool &DuplicatedToPred);
|
bool &DuplicatedToLPred);
|
||||||
bool hasBetterLayoutPredecessor(
|
bool hasBetterLayoutPredecessor(
|
||||||
const MachineBasicBlock *BB, const MachineBasicBlock *Succ,
|
const MachineBasicBlock *BB, const MachineBasicBlock *Succ,
|
||||||
const BlockChain &SuccChain, BranchProbability SuccProb,
|
const BlockChain &SuccChain, BranchProbability SuccProb,
|
||||||
@ -474,7 +474,7 @@ class MachineBlockPlacement : public MachineFunctionPass {
|
|||||||
/// fallthroughs.
|
/// fallthroughs.
|
||||||
bool isProfitableToTailDup(
|
bool isProfitableToTailDup(
|
||||||
const MachineBasicBlock *BB, const MachineBasicBlock *Succ,
|
const MachineBasicBlock *BB, const MachineBasicBlock *Succ,
|
||||||
BranchProbability AdjustedSumProb,
|
BranchProbability QProb,
|
||||||
const BlockChain &Chain, const BlockFilterSet *BlockFilter);
|
const BlockChain &Chain, const BlockFilterSet *BlockFilter);
|
||||||
|
|
||||||
/// Check for a trellis layout.
|
/// Check for a trellis layout.
|
||||||
|
@ -216,7 +216,7 @@ namespace {
|
|||||||
DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren,
|
DenseMap<MachineDomTreeNode *, unsigned> &OpenChildren,
|
||||||
DenseMap<MachineDomTreeNode *, MachineDomTreeNode *> &ParentMap);
|
DenseMap<MachineDomTreeNode *, MachineDomTreeNode *> &ParentMap);
|
||||||
|
|
||||||
void HoistOutOfLoop(MachineDomTreeNode *LoopHeaderNode);
|
void HoistOutOfLoop(MachineDomTreeNode *HeaderN);
|
||||||
|
|
||||||
void HoistRegion(MachineDomTreeNode *N, bool IsHeader);
|
void HoistRegion(MachineDomTreeNode *N, bool IsHeader);
|
||||||
|
|
||||||
|
@ -434,7 +434,7 @@ private:
|
|||||||
unsigned InstStageNum,
|
unsigned InstStageNum,
|
||||||
SMSchedule &Schedule);
|
SMSchedule &Schedule);
|
||||||
void updateInstruction(MachineInstr *NewMI, bool LastDef,
|
void updateInstruction(MachineInstr *NewMI, bool LastDef,
|
||||||
unsigned CurStageNum, unsigned InstStageNum,
|
unsigned CurStageNum, unsigned InstrStageNum,
|
||||||
SMSchedule &Schedule, ValueMapTy *VRMap);
|
SMSchedule &Schedule, ValueMapTy *VRMap);
|
||||||
MachineInstr *findDefInLoop(unsigned Reg);
|
MachineInstr *findDefInLoop(unsigned Reg);
|
||||||
unsigned getPrevMapVal(unsigned StageNum, unsigned PhiStage, unsigned LoopVal,
|
unsigned getPrevMapVal(unsigned StageNum, unsigned PhiStage, unsigned LoopVal,
|
||||||
@ -710,7 +710,7 @@ public:
|
|||||||
void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
|
void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
|
||||||
std::deque<SUnit *> &Insts);
|
std::deque<SUnit *> &Insts);
|
||||||
bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi);
|
bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi);
|
||||||
bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Inst,
|
bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def,
|
||||||
MachineOperand &MO);
|
MachineOperand &MO);
|
||||||
void print(raw_ostream &os) const;
|
void print(raw_ostream &os) const;
|
||||||
void dump() const;
|
void dump() const;
|
||||||
|
@ -251,16 +251,16 @@ namespace {
|
|||||||
void report_context_liverange(const LiveRange &LR) const;
|
void report_context_liverange(const LiveRange &LR) const;
|
||||||
void report_context_lanemask(LaneBitmask LaneMask) const;
|
void report_context_lanemask(LaneBitmask LaneMask) const;
|
||||||
void report_context_vreg(unsigned VReg) const;
|
void report_context_vreg(unsigned VReg) const;
|
||||||
void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
|
void report_context_vreg_regunit(unsigned VRegOrUnit) const;
|
||||||
|
|
||||||
void verifyInlineAsm(const MachineInstr *MI);
|
void verifyInlineAsm(const MachineInstr *MI);
|
||||||
|
|
||||||
void checkLiveness(const MachineOperand *MO, unsigned MONum);
|
void checkLiveness(const MachineOperand *MO, unsigned MONum);
|
||||||
void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
|
void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
|
||||||
SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
|
SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
|
||||||
LaneBitmask LaneMask = LaneBitmask::getNone());
|
LaneBitmask LaneMask = LaneBitmask::getNone());
|
||||||
void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
|
void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
|
||||||
SlotIndex DefIdx, const LiveRange &LR, unsigned Reg,
|
SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
|
||||||
LaneBitmask LaneMask = LaneBitmask::getNone());
|
LaneBitmask LaneMask = LaneBitmask::getNone());
|
||||||
|
|
||||||
void markReachable(const MachineBasicBlock *MBB);
|
void markReachable(const MachineBasicBlock *MBB);
|
||||||
|
@ -45,7 +45,7 @@ namespace {
|
|||||||
initializeOptimizePHIsPass(*PassRegistry::getPassRegistry());
|
initializeOptimizePHIsPass(*PassRegistry::getPassRegistry());
|
||||||
}
|
}
|
||||||
|
|
||||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
bool runOnMachineFunction(MachineFunction &Fn) override;
|
||||||
|
|
||||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||||
AU.setPreservesCFG();
|
AU.setPreservesCFG();
|
||||||
|
@ -75,7 +75,7 @@ namespace {
|
|||||||
initializePHIEliminationPass(*PassRegistry::getPassRegistry());
|
initializePHIEliminationPass(*PassRegistry::getPassRegistry());
|
||||||
}
|
}
|
||||||
|
|
||||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||||
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
@ -91,7 +91,7 @@ namespace {
|
|||||||
/// register which is used in a PHI node. We map that to the BB the
|
/// register which is used in a PHI node. We map that to the BB the
|
||||||
/// vreg is coming from. This is used later to determine when the vreg
|
/// vreg is coming from. This is used later to determine when the vreg
|
||||||
/// is killed in the BB.
|
/// is killed in the BB.
|
||||||
void analyzePHINodes(const MachineFunction& Fn);
|
void analyzePHINodes(const MachineFunction& MF);
|
||||||
|
|
||||||
/// Split critical edges where necessary for good coalescer performance.
|
/// Split critical edges where necessary for good coalescer performance.
|
||||||
bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
|
bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||||
|
@ -44,7 +44,7 @@ public:
|
|||||||
|
|
||||||
void getAnalysisUsage(AnalysisUsage &au) const override;
|
void getAnalysisUsage(AnalysisUsage &au) const override;
|
||||||
|
|
||||||
bool runOnMachineFunction(MachineFunction &fn) override;
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||||
};
|
};
|
||||||
} // end anonymous namespace
|
} // end anonymous namespace
|
||||||
|
|
||||||
|
@ -179,7 +179,7 @@ namespace {
|
|||||||
}
|
}
|
||||||
|
|
||||||
private:
|
private:
|
||||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||||
void allocateBasicBlock(MachineBasicBlock &MBB);
|
void allocateBasicBlock(MachineBasicBlock &MBB);
|
||||||
void handleThroughOperands(MachineInstr &MI,
|
void handleThroughOperands(MachineInstr &MI,
|
||||||
SmallVectorImpl<unsigned> &VirtDead);
|
SmallVectorImpl<unsigned> &VirtDead);
|
||||||
@ -206,7 +206,7 @@ namespace {
|
|||||||
return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
|
return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
|
||||||
}
|
}
|
||||||
|
|
||||||
LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, MCPhysReg PhysReg);
|
LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg);
|
||||||
LiveRegMap::iterator allocVirtReg(MachineInstr &MI, LiveRegMap::iterator,
|
LiveRegMap::iterator allocVirtReg(MachineInstr &MI, LiveRegMap::iterator,
|
||||||
unsigned Hint);
|
unsigned Hint);
|
||||||
LiveRegMap::iterator defineVirtReg(MachineInstr &MI, unsigned OpNum,
|
LiveRegMap::iterator defineVirtReg(MachineInstr &MI, unsigned OpNum,
|
||||||
|
@ -462,7 +462,7 @@ private:
|
|||||||
bool calcCompactRegion(GlobalSplitCandidate&);
|
bool calcCompactRegion(GlobalSplitCandidate&);
|
||||||
void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
|
void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
|
||||||
void calcGapWeights(unsigned, SmallVectorImpl<float>&);
|
void calcGapWeights(unsigned, SmallVectorImpl<float>&);
|
||||||
unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
|
unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg);
|
||||||
bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
|
bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
|
||||||
bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
|
bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
|
||||||
bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
|
bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
|
||||||
|
@ -162,7 +162,7 @@ namespace {
|
|||||||
/// was successfully coalesced away. If it is not currently possible to
|
/// was successfully coalesced away. If it is not currently possible to
|
||||||
/// coalesce this interval, but it may be possible if other things get
|
/// coalesce this interval, but it may be possible if other things get
|
||||||
/// coalesced, then it returns true by reference in 'Again'.
|
/// coalesced, then it returns true by reference in 'Again'.
|
||||||
bool joinCopy(MachineInstr *TheCopy, bool &Again);
|
bool joinCopy(MachineInstr *CopyMI, bool &Again);
|
||||||
|
|
||||||
/// Attempt to join these two intervals. On failure, this
|
/// Attempt to join these two intervals. On failure, this
|
||||||
/// returns false. The output "SrcInt" will not have been modified, so we
|
/// returns false. The output "SrcInt" will not have been modified, so we
|
||||||
@ -2126,7 +2126,7 @@ class JoinVals {
|
|||||||
/// Find the ultimate value that VNI was copied from.
|
/// Find the ultimate value that VNI was copied from.
|
||||||
std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
|
std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
|
||||||
|
|
||||||
bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const;
|
bool valuesIdentical(VNInfo *Value0, VNInfo *Value1, const JoinVals &Other) const;
|
||||||
|
|
||||||
/// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
|
/// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
|
||||||
/// Return a conflict resolution when possible, but leave the hard cases as
|
/// Return a conflict resolution when possible, but leave the hard cases as
|
||||||
|
@ -61,7 +61,7 @@ namespace llvm {
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
std::string getNodeLabel(const SUnit *Node, const ScheduleDAG *Graph);
|
std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *Graph);
|
||||||
static std::string getNodeAttributes(const SUnit *N,
|
static std::string getNodeAttributes(const SUnit *N,
|
||||||
const ScheduleDAG *Graph) {
|
const ScheduleDAG *Graph) {
|
||||||
return "shape=Mrecord";
|
return "shape=Mrecord";
|
||||||
|
@ -310,9 +310,9 @@ namespace {
|
|||||||
SDValue visitUMULO(SDNode *N);
|
SDValue visitUMULO(SDNode *N);
|
||||||
SDValue visitIMINMAX(SDNode *N);
|
SDValue visitIMINMAX(SDNode *N);
|
||||||
SDValue visitAND(SDNode *N);
|
SDValue visitAND(SDNode *N);
|
||||||
SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
|
SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
|
||||||
SDValue visitOR(SDNode *N);
|
SDValue visitOR(SDNode *N);
|
||||||
SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
|
SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
|
||||||
SDValue visitXOR(SDNode *N);
|
SDValue visitXOR(SDNode *N);
|
||||||
SDValue SimplifyVBinOp(SDNode *N);
|
SDValue SimplifyVBinOp(SDNode *N);
|
||||||
SDValue visitSHL(SDNode *N);
|
SDValue visitSHL(SDNode *N);
|
||||||
@ -392,8 +392,8 @@ namespace {
|
|||||||
SDValue visitFMULForFMADistributiveCombine(SDNode *N);
|
SDValue visitFMULForFMADistributiveCombine(SDNode *N);
|
||||||
|
|
||||||
SDValue XformToShuffleWithZero(SDNode *N);
|
SDValue XformToShuffleWithZero(SDNode *N);
|
||||||
SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue LHS,
|
SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
|
||||||
SDValue RHS);
|
SDValue N1);
|
||||||
|
|
||||||
SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
|
SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
|
||||||
|
|
||||||
@ -431,14 +431,14 @@ namespace {
|
|||||||
SDValue BuildSDIV(SDNode *N);
|
SDValue BuildSDIV(SDNode *N);
|
||||||
SDValue BuildSDIVPow2(SDNode *N);
|
SDValue BuildSDIVPow2(SDNode *N);
|
||||||
SDValue BuildUDIV(SDNode *N);
|
SDValue BuildUDIV(SDNode *N);
|
||||||
SDValue BuildLogBase2(SDValue Op, const SDLoc &DL);
|
SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
|
||||||
SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags Flags);
|
SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags Flags);
|
||||||
SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
|
SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
|
||||||
SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
|
SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
|
||||||
SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
|
SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
|
||||||
SDValue buildSqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations,
|
SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
|
||||||
SDNodeFlags Flags, bool Reciprocal);
|
SDNodeFlags Flags, bool Reciprocal);
|
||||||
SDValue buildSqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations,
|
SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
|
||||||
SDNodeFlags Flags, bool Reciprocal);
|
SDNodeFlags Flags, bool Reciprocal);
|
||||||
SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
|
SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
|
||||||
bool DemandHighBits = true);
|
bool DemandHighBits = true);
|
||||||
@ -460,7 +460,7 @@ namespace {
|
|||||||
SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
|
SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
|
||||||
ArrayRef<int> VectorMask, SDValue VecIn1,
|
ArrayRef<int> VectorMask, SDValue VecIn1,
|
||||||
SDValue VecIn2, unsigned LeftIdx);
|
SDValue VecIn2, unsigned LeftIdx);
|
||||||
SDValue matchVSelectOpSizesWithSetCC(SDNode *N);
|
SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
|
||||||
|
|
||||||
/// Walk up chain skipping non-aliasing memory nodes,
|
/// Walk up chain skipping non-aliasing memory nodes,
|
||||||
/// looking for aliasing nodes and adding them to the Aliases vector.
|
/// looking for aliasing nodes and adding them to the Aliases vector.
|
||||||
@ -519,8 +519,8 @@ namespace {
|
|||||||
|
|
||||||
/// Used by BackwardsPropagateMask to find suitable loads.
|
/// Used by BackwardsPropagateMask to find suitable loads.
|
||||||
bool SearchForAndLoads(SDNode *N, SmallPtrSetImpl<LoadSDNode*> &Loads,
|
bool SearchForAndLoads(SDNode *N, SmallPtrSetImpl<LoadSDNode*> &Loads,
|
||||||
SmallPtrSetImpl<SDNode*> &NodeWithConsts,
|
SmallPtrSetImpl<SDNode*> &NodesWithConsts,
|
||||||
ConstantSDNode *Mask, SDNode *&UncombinedNode);
|
ConstantSDNode *Mask, SDNode *&NodeToMask);
|
||||||
/// Attempt to propagate a given AND node back to load leaves so that they
|
/// Attempt to propagate a given AND node back to load leaves so that they
|
||||||
/// can be combined into narrow loads.
|
/// can be combined into narrow loads.
|
||||||
bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG);
|
bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG);
|
||||||
@ -561,7 +561,7 @@ namespace {
|
|||||||
/// This optimization uses wide integers or vectors when possible.
|
/// This optimization uses wide integers or vectors when possible.
|
||||||
/// \return number of stores that were merged into a merged store (the
|
/// \return number of stores that were merged into a merged store (the
|
||||||
/// affected nodes are stored as a prefix in \p StoreNodes).
|
/// affected nodes are stored as a prefix in \p StoreNodes).
|
||||||
bool MergeConsecutiveStores(StoreSDNode *N);
|
bool MergeConsecutiveStores(StoreSDNode *St);
|
||||||
|
|
||||||
/// Try to transform a truncation where C is a constant:
|
/// Try to transform a truncation where C is a constant:
|
||||||
/// (trunc (and X, C)) -> (and (trunc X), (trunc C))
|
/// (trunc (and X, C)) -> (and (trunc X), (trunc C))
|
||||||
|
@ -167,7 +167,7 @@ private:
|
|||||||
SDValue NewIntValue) const;
|
SDValue NewIntValue) const;
|
||||||
SDValue ExpandFCOPYSIGN(SDNode *Node) const;
|
SDValue ExpandFCOPYSIGN(SDNode *Node) const;
|
||||||
SDValue ExpandFABS(SDNode *Node) const;
|
SDValue ExpandFABS(SDNode *Node) const;
|
||||||
SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
|
SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
|
||||||
const SDLoc &dl);
|
const SDLoc &dl);
|
||||||
SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
|
SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
|
||||||
const SDLoc &dl);
|
const SDLoc &dl);
|
||||||
|
@ -209,7 +209,7 @@ private:
|
|||||||
SDNode *AnalyzeNewNode(SDNode *N);
|
SDNode *AnalyzeNewNode(SDNode *N);
|
||||||
void AnalyzeNewValue(SDValue &Val);
|
void AnalyzeNewValue(SDValue &Val);
|
||||||
void PerformExpensiveChecks();
|
void PerformExpensiveChecks();
|
||||||
void RemapId(TableId &N);
|
void RemapId(TableId &Id);
|
||||||
void RemapValue(SDValue &V);
|
void RemapValue(SDValue &V);
|
||||||
|
|
||||||
// Common routines.
|
// Common routines.
|
||||||
@ -332,7 +332,7 @@ private:
|
|||||||
SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
|
SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
|
||||||
|
|
||||||
// Integer Operand Promotion.
|
// Integer Operand Promotion.
|
||||||
bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
|
bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
|
||||||
SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
|
SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
|
||||||
SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
|
SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
|
||||||
SDValue PromoteIntOp_BITCAST(SDNode *N);
|
SDValue PromoteIntOp_BITCAST(SDNode *N);
|
||||||
@ -423,7 +423,7 @@ private:
|
|||||||
bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
|
bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
|
|
||||||
// Integer Operand Expansion.
|
// Integer Operand Expansion.
|
||||||
bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
|
bool ExpandIntegerOperand(SDNode *N, unsigned OpNo);
|
||||||
SDValue ExpandIntOp_BR_CC(SDNode *N);
|
SDValue ExpandIntOp_BR_CC(SDNode *N);
|
||||||
SDValue ExpandIntOp_SELECT_CC(SDNode *N);
|
SDValue ExpandIntOp_SELECT_CC(SDNode *N);
|
||||||
SDValue ExpandIntOp_SETCC(SDNode *N);
|
SDValue ExpandIntOp_SETCC(SDNode *N);
|
||||||
@ -579,7 +579,7 @@ private:
|
|||||||
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
|
|
||||||
// Float Operand Expansion.
|
// Float Operand Expansion.
|
||||||
bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
|
bool ExpandFloatOperand(SDNode *N, unsigned OpNo);
|
||||||
SDValue ExpandFloatOp_BR_CC(SDNode *N);
|
SDValue ExpandFloatOp_BR_CC(SDNode *N);
|
||||||
SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
|
SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
|
||||||
SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
|
SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
|
||||||
@ -620,7 +620,7 @@ private:
|
|||||||
SDValue PromoteFloatRes_UNDEF(SDNode *N);
|
SDValue PromoteFloatRes_UNDEF(SDNode *N);
|
||||||
SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);
|
SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);
|
||||||
|
|
||||||
bool PromoteFloatOperand(SDNode *N, unsigned ResNo);
|
bool PromoteFloatOperand(SDNode *N, unsigned OpNo);
|
||||||
SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);
|
SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);
|
||||||
SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
|
SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
|
||||||
SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);
|
SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);
|
||||||
@ -645,7 +645,7 @@ private:
|
|||||||
void SetScalarizedVector(SDValue Op, SDValue Result);
|
void SetScalarizedVector(SDValue Op, SDValue Result);
|
||||||
|
|
||||||
// Vector Result Scalarization: <1 x ty> -> ty.
|
// Vector Result Scalarization: <1 x ty> -> ty.
|
||||||
void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
|
void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
|
||||||
SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
|
SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
|
||||||
SDValue ScalarizeVecRes_BinOp(SDNode *N);
|
SDValue ScalarizeVecRes_BinOp(SDNode *N);
|
||||||
SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
|
SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
|
||||||
@ -694,7 +694,7 @@ private:
|
|||||||
void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
|
void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
|
||||||
|
|
||||||
// Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
|
// Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
|
||||||
void SplitVectorResult(SDNode *N, unsigned OpNo);
|
void SplitVectorResult(SDNode *N, unsigned ResNo);
|
||||||
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
@ -710,9 +710,9 @@ private:
|
|||||||
void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_MLOAD(MaskedLoadSDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_MGATHER(MaskedGatherSDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
|
void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
|
||||||
void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
|
void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
|
||||||
@ -732,7 +732,7 @@ private:
|
|||||||
SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
|
SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
|
||||||
SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
|
SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
|
||||||
SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
|
SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
|
||||||
SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
|
SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *MGT, unsigned OpNo);
|
||||||
SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
|
SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
|
||||||
SDValue SplitVecOp_VSETCC(SDNode *N);
|
SDValue SplitVecOp_VSETCC(SDNode *N);
|
||||||
SDValue SplitVecOp_FP_ROUND(SDNode *N);
|
SDValue SplitVecOp_FP_ROUND(SDNode *N);
|
||||||
|
@ -88,7 +88,7 @@ class InstrItineraryData;
|
|||||||
/// Clone - Creates a clone of the specified SUnit. It does not copy the
|
/// Clone - Creates a clone of the specified SUnit. It does not copy the
|
||||||
/// predecessors / successors info nor the temporary scheduling states.
|
/// predecessors / successors info nor the temporary scheduling states.
|
||||||
///
|
///
|
||||||
SUnit *Clone(SUnit *N);
|
SUnit *Clone(SUnit *Old);
|
||||||
|
|
||||||
/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
|
/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
|
||||||
/// are input. This SUnit graph is similar to the SelectionDAG, but
|
/// are input. This SUnit graph is similar to the SelectionDAG, but
|
||||||
|
@ -712,13 +712,13 @@ public:
|
|||||||
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
|
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
|
||||||
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
||||||
MachineBasicBlock *SwitchBB,
|
MachineBasicBlock *SwitchBB,
|
||||||
Instruction::BinaryOps Opc, BranchProbability TW,
|
Instruction::BinaryOps Opc, BranchProbability TProb,
|
||||||
BranchProbability FW, bool InvertCond);
|
BranchProbability FProb, bool InvertCond);
|
||||||
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
|
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
|
||||||
MachineBasicBlock *FBB,
|
MachineBasicBlock *FBB,
|
||||||
MachineBasicBlock *CurBB,
|
MachineBasicBlock *CurBB,
|
||||||
MachineBasicBlock *SwitchBB,
|
MachineBasicBlock *SwitchBB,
|
||||||
BranchProbability TW, BranchProbability FW,
|
BranchProbability TProb, BranchProbability FProb,
|
||||||
bool InvertCond);
|
bool InvertCond);
|
||||||
bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
|
bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
|
||||||
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
|
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
|
||||||
@ -790,11 +790,11 @@ public:
|
|||||||
};
|
};
|
||||||
|
|
||||||
/// Lower \p SLI into a STATEPOINT instruction.
|
/// Lower \p SLI into a STATEPOINT instruction.
|
||||||
SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SLI);
|
SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI);
|
||||||
|
|
||||||
// This function is responsible for the whole statepoint lowering process.
|
// This function is responsible for the whole statepoint lowering process.
|
||||||
// It uniformly handles invoke and call statepoints.
|
// It uniformly handles invoke and call statepoints.
|
||||||
void LowerStatepoint(ImmutableStatepoint Statepoint,
|
void LowerStatepoint(ImmutableStatepoint ISP,
|
||||||
const BasicBlock *EHPadBB = nullptr);
|
const BasicBlock *EHPadBB = nullptr);
|
||||||
|
|
||||||
void LowerCallSiteWithDeoptBundle(ImmutableCallSite CS, SDValue Callee,
|
void LowerCallSiteWithDeoptBundle(ImmutableCallSite CS, SDValue Callee,
|
||||||
@ -897,7 +897,7 @@ private:
|
|||||||
|
|
||||||
void visitExtractValue(const User &I);
|
void visitExtractValue(const User &I);
|
||||||
void visitInsertValue(const User &I);
|
void visitInsertValue(const User &I);
|
||||||
void visitLandingPad(const LandingPadInst &I);
|
void visitLandingPad(const LandingPadInst &LP);
|
||||||
|
|
||||||
void visitGetElementPtr(const User &I);
|
void visitGetElementPtr(const User &I);
|
||||||
void visitSelect(const User &I);
|
void visitSelect(const User &I);
|
||||||
@ -942,7 +942,7 @@ private:
|
|||||||
const BasicBlock *EHPadBB = nullptr);
|
const BasicBlock *EHPadBB = nullptr);
|
||||||
|
|
||||||
// These two are implemented in StatepointLowering.cpp
|
// These two are implemented in StatepointLowering.cpp
|
||||||
void visitGCRelocate(const GCRelocateInst &I);
|
void visitGCRelocate(const GCRelocateInst &Relocate);
|
||||||
void visitGCResult(const GCResultInst &I);
|
void visitGCResult(const GCResultInst &I);
|
||||||
|
|
||||||
void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
|
void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
|
||||||
@ -1052,7 +1052,7 @@ struct RegsForValue {
|
|||||||
/// Add this value to the specified inlineasm node operand list. This adds the
|
/// Add this value to the specified inlineasm node operand list. This adds the
|
||||||
/// code marker, matching input operand index (if applicable), and includes
|
/// code marker, matching input operand index (if applicable), and includes
|
||||||
/// the number of values added into it.
|
/// the number of values added into it.
|
||||||
void AddInlineAsmOperands(unsigned Kind, bool HasMatching,
|
void AddInlineAsmOperands(unsigned Code, bool HasMatching,
|
||||||
unsigned MatchingIdx, const SDLoc &dl,
|
unsigned MatchingIdx, const SDLoc &dl,
|
||||||
SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
|
SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
|
||||||
|
|
||||||
|
@ -421,7 +421,7 @@ private:
|
|||||||
|
|
||||||
SlotIndex buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg,
|
SlotIndex buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg,
|
||||||
MachineBasicBlock &MB, MachineBasicBlock::iterator InsertBefore,
|
MachineBasicBlock &MB, MachineBasicBlock::iterator InsertBefore,
|
||||||
unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex PrevCopy);
|
unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def);
|
||||||
|
|
||||||
public:
|
public:
|
||||||
/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
|
/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
|
||||||
|
@ -445,7 +445,7 @@ public:
|
|||||||
}
|
}
|
||||||
|
|
||||||
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
||||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
bool runOnMachineFunction(MachineFunction &Func) override;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
/// Used in collectMarkers
|
/// Used in collectMarkers
|
||||||
|
Loading…
Reference in New Issue
Block a user