[SystemZ] Add hexadecimal floating-point instructions

This adds assembler / disassembler support for the hexadecimal floating-point instructions. Since the Linux ABI does not use any hex float data types, these are not useful for codegen. llvm-svn: 304202
2024-10-19 11:02:59 +02:00 · 2017-05-30 10:13:23 +00:00 · 2017-05-30 10:13:23 +00:00 · c793765ccb
commit c793765ccb
parent 15e4c4b782
10 changed files with 4117 additions and 19 deletions
--- a/lib/Target/SystemZ/SystemZ.td
+++ b/lib/Target/SystemZ/SystemZ.td
@ -54,6 +54,7 @@ include "SystemZInstrFormats.td"
 include "SystemZInstrInfo.td"
 include "SystemZInstrVector.td"
 include "SystemZInstrFP.td"
+include "SystemZInstrHFP.td"

 def SystemZInstrInfo : InstrInfo {}

--- a/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/lib/Target/SystemZ/SystemZInstrFP.td
@ -121,7 +121,8 @@ let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
  defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;

  // For z13 we prefer LDE over LE to avoid partial register dependencies.
-  def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;
+  let isCodeGenOnly = 1 in
+    def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;

  // These instructions are split after register allocation, so we don't
  // want a custom inserter.
@ -437,18 +438,18 @@ def : Pat<(fmul (f128 (fpextend FP64:$src1)),
                bdxaddr12only:$addr)>;

 // Fused multiply-add.
-def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32>;
-def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64>;
+def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32, FP32>;
+def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64, FP64>;

-def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
-def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
+def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, FP32, load, 4>;
+def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, FP64, load, 8>;

 // Fused multiply-subtract.
-def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32>;
-def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64>;
+def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32, FP32>;
+def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64, FP64>;

-def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
-def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
+def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, FP32, load, 4>;
+def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, FP64, load, 8>;

 // Division.
 def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32,  FP32>;
--- a/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/lib/Target/SystemZ/SystemZInstrFormats.td
@ -2752,6 +2752,15 @@ class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
  let DisableEncoding = "$R1src";
 }

+class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+                RegisterOperand cls1, RegisterOperand cls2>
+  : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
+            mnemonic#"\t$R1, $R3, $R2",
+            [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
+  let OpKey = mnemonic#cls;
+  let OpType = "reg";
+}
+
 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                 RegisterOperand cls1, RegisterOperand cls2,
                 RegisterOperand cls3>
@ -2987,6 +2996,18 @@ class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
  let M3 = 0;
 }

+class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+                RegisterOperand cls1, RegisterOperand cls2,
+                SDPatternOperator load, bits<5> bytes>
+  : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
+            mnemonic#"\t$R1, $R3, $XBD2",
+            [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
+  let OpKey = mnemonic#"r"#cls;
+  let OpType = "mem";
+  let mayLoad = 1;
+  let AccessBytes = bytes;
+}
+
 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
                AddressingMode mode = bdxaddr20only>
@ -3597,11 +3618,11 @@ class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
             (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
             mnemonic#"\t$R1, $M3, $R2, $M4", []>;

-class TernaryRRD<string mnemonic, bits<16> opcode,
-                 SDPatternOperator operator, RegisterOperand cls>
-  : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
+class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+                 RegisterOperand cls1, RegisterOperand cls2>
+  : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
            mnemonic#"\t$R1, $R3, $R2",
-            [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
+            [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
  let OpKey = mnemonic#cls;
  let OpType = "reg";
  let Constraints = "$R1 = $R1src";
@ -3661,12 +3682,13 @@ class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
 }

 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
-                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
-  : InstRXF<opcode, (outs cls:$R1),
-            (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
+                 RegisterOperand cls1, RegisterOperand cls2,
+                 SDPatternOperator load, bits<5> bytes>
+  : InstRXF<opcode, (outs cls1:$R1),
+            (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
            mnemonic#"\t$R1, $R3, $XBD2",
-            [(set cls:$R1, (operator cls:$R1src, cls:$R3,
-                                     (load bdxaddr12only:$XBD2)))]> {
+            [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
+                                      (load bdxaddr12only:$XBD2)))]> {
  let OpKey = mnemonic#"r"#cls;
  let OpType = "mem";
  let Constraints = "$R1 = $R1src";
--- a/lib/Target/SystemZ/SystemZInstrHFP.td
+++ b/lib/Target/SystemZ/SystemZInstrHFP.td
@ -0,0 +1,240 @@
+//==- SystemZInstrHFP.td - Floating-point SystemZ instructions -*- tblgen-*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// The instructions in this file implement SystemZ hexadecimal floating-point
+// arithmetic.  Since this format is not mapped to any source-language data
+// type, these instructions are not used for code generation, but are provided
+// for use with the assembler and disassembler only.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Move instructions
+//===----------------------------------------------------------------------===//
+
+// Load and test.
+let Defs = [CC] in {
+  def LTER : UnaryRR <"lter", 0x32,   null_frag, FP32,  FP32>;
+  def LTDR : UnaryRR <"ltdr", 0x22,   null_frag, FP64,  FP64>;
+  def LTXR : UnaryRRE<"ltxr", 0xB362, null_frag, FP128, FP128>;
+}
+
+//===----------------------------------------------------------------------===//
+// Conversion instructions
+//===----------------------------------------------------------------------===//
+
+// Convert floating-point values to narrower representations.
+def LEDR : UnaryRR <"ledr", 0x35,   null_frag, FP32, FP64>;
+def LEXR : UnaryRRE<"lexr", 0xB366, null_frag, FP32, FP128>;
+def LDXR : UnaryRR <"ldxr", 0x25,   null_frag, FP64, FP128>;
+let isAsmParserOnly = 1 in {
+  def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
+  def LRDR : UnaryRR <"lrdr", 0x25, null_frag, FP64, FP128>;
+}
+
+// Extend floating-point values to wider representations.
+def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64,  FP32>;
+def LXER : UnaryRRE<"lxer", 0xB326, null_frag, FP128, FP32>;
+def LXDR : UnaryRRE<"lxdr", 0xB325, null_frag, FP128, FP64>;
+
+def LDE : UnaryRXE<"lde", 0xED24, null_frag, FP64,  4>;
+def LXE : UnaryRXE<"lxe", 0xED26, null_frag, FP128, 4>;
+def LXD : UnaryRXE<"lxd", 0xED25, null_frag, FP128, 8>;
+
+// Convert a signed integer register value to a floating-point one.
+def CEFR : UnaryRRE<"cefr", 0xB3B4, null_frag, FP32,  GR32>;
+def CDFR : UnaryRRE<"cdfr", 0xB3B5, null_frag, FP64,  GR32>;
+def CXFR : UnaryRRE<"cxfr", 0xB3B6, null_frag, FP128, GR32>;
+
+def CEGR : UnaryRRE<"cegr", 0xB3C4, null_frag, FP32,  GR64>;
+def CDGR : UnaryRRE<"cdgr", 0xB3C5, null_frag, FP64,  GR64>;
+def CXGR : UnaryRRE<"cxgr", 0xB3C6, null_frag, FP128, GR64>;
+
+// Convert a floating-point register value to a signed integer value,
+// with the second operand (modifier M3) specifying the rounding mode.
+let Defs = [CC] in {
+  def CFER : BinaryRRFe<"cfer", 0xB3B8, GR32, FP32>;
+  def CFDR : BinaryRRFe<"cfdr", 0xB3B9, GR32, FP64>;
+  def CFXR : BinaryRRFe<"cfxr", 0xB3BA, GR32, FP128>;
+
+  def CGER : BinaryRRFe<"cger", 0xB3C8, GR64, FP32>;
+  def CGDR : BinaryRRFe<"cgdr", 0xB3C9, GR64, FP64>;
+  def CGXR : BinaryRRFe<"cgxr", 0xB3CA, GR64, FP128>;
+}
+
+// Convert BFP to HFP.
+let Defs = [CC] in {
+  def THDER : UnaryRRE<"thder", 0xB358, null_frag, FP64, FP32>;
+  def THDR  : UnaryRRE<"thdr",  0xB359, null_frag, FP64, FP64>;
+}
+
+// Convert HFP to BFP.
+let Defs = [CC] in {
+  def TBEDR : BinaryRRFe<"tbedr", 0xB350, FP32, FP64>;
+  def TBDR  : BinaryRRFe<"tbdr",  0xB351, FP64, FP64>;
+}
+
+
+//===----------------------------------------------------------------------===//
+// Unary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Negation (Load Complement).
+let Defs = [CC] in {
+  def LCER : UnaryRR <"lcer", 0x33,   null_frag, FP32,  FP32>;
+  def LCDR : UnaryRR <"lcdr", 0x23,   null_frag, FP64,  FP64>;
+  def LCXR : UnaryRRE<"lcxr", 0xB363, null_frag, FP128, FP128>;
+}
+
+// Absolute value (Load Positive).
+let Defs = [CC] in {
+  def LPER : UnaryRR <"lper", 0x30,   null_frag, FP32,  FP32>;
+  def LPDR : UnaryRR <"lpdr", 0x20,   null_frag, FP64,  FP64>;
+  def LPXR : UnaryRRE<"lpxr", 0xB360, null_frag, FP128, FP128>;
+}
+
+// Negative absolute value (Load Negative).
+let Defs = [CC] in {
+  def LNER : UnaryRR <"lner", 0x31,   null_frag, FP32,  FP32>;
+  def LNDR : UnaryRR <"lndr", 0x21,   null_frag, FP64,  FP64>;
+  def LNXR : UnaryRRE<"lnxr", 0xB361, null_frag, FP128, FP128>;
+}
+
+// Halve.
+def HER : UnaryRR <"her", 0x34, null_frag, FP32, FP32>;
+def HDR : UnaryRR <"hdr", 0x24, null_frag, FP64, FP64>;
+
+// Square root.
+def SQER : UnaryRRE<"sqer", 0xB245, null_frag, FP32,  FP32>;
+def SQDR : UnaryRRE<"sqdr", 0xB244, null_frag, FP64,  FP64>;
+def SQXR : UnaryRRE<"sqxr", 0xB336, null_frag, FP128, FP128>;
+
+def SQE : UnaryRXE<"sqe", 0xED34, null_frag, FP32, 4>;
+def SQD : UnaryRXE<"sqd", 0xED35, null_frag, FP64, 8>;
+
+// Round to an integer (rounding towards zero).
+def FIER : UnaryRRE<"fier", 0xB377, null_frag, FP32,  FP32>;
+def FIDR : UnaryRRE<"fidr", 0xB37F, null_frag, FP64,  FP64>;
+def FIXR : UnaryRRE<"fixr", 0xB367, null_frag, FP128, FP128>;
+
+
+//===----------------------------------------------------------------------===//
+// Binary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Addition.
+let Defs = [CC] in {
+  let isCommutable = 1 in {
+    def AER : BinaryRR<"aer", 0x3A, null_frag, FP32,  FP32>;
+    def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64,  FP64>;
+    def AXR : BinaryRR<"axr", 0x36, null_frag, FP128, FP128>;
+  }
+  def AE : BinaryRX<"ae", 0x7A, null_frag, FP32, load, 4>;
+  def AD : BinaryRX<"ad", 0x6A, null_frag, FP64, load, 8>;
+}
+
+// Addition (unnormalized).
+let Defs = [CC] in {
+  let isCommutable = 1 in {
+    def AUR : BinaryRR<"aur", 0x3E, null_frag, FP32, FP32>;
+    def AWR : BinaryRR<"awr", 0x2E, null_frag, FP64, FP64>;
+  }
+  def AU : BinaryRX<"au", 0x7E, null_frag, FP32, load, 4>;
+  def AW : BinaryRX<"aw", 0x6E, null_frag, FP64, load, 8>;
+}
+
+// Subtraction.
+let Defs = [CC] in {
+  def SER : BinaryRR<"ser", 0x3B, null_frag, FP32,  FP32>;
+  def SDR : BinaryRR<"sdr", 0x2B, null_frag, FP64,  FP64>;
+  def SXR : BinaryRR<"sxr", 0x37, null_frag, FP128, FP128>;
+
+  def SE : BinaryRX<"se", 0x7B, null_frag, FP32, load, 4>;
+  def SD : BinaryRX<"sd", 0x6B, null_frag, FP64, load, 8>;
+}
+
+// Subtraction (unnormalized).
+let Defs = [CC] in {
+  def SUR : BinaryRR<"sur", 0x3F, null_frag, FP32, FP32>;
+  def SWR : BinaryRR<"swr", 0x2F, null_frag, FP64, FP64>;
+
+  def SU : BinaryRX<"su", 0x7F, null_frag, FP32, load, 4>;
+  def SW : BinaryRX<"sw", 0x6F, null_frag, FP64, load, 8>;
+}
+
+// Multiplication.
+let isCommutable = 1 in {
+  def MEER : BinaryRRE<"meer", 0xB337, null_frag, FP32,  FP32>;
+  def MDR  : BinaryRR <"mdr",  0x2C,   null_frag, FP64,  FP64>;
+  def MXR  : BinaryRR <"mxr",  0x26,   null_frag, FP128, FP128>;
+}
+def MEE : BinaryRXE<"mee", 0xED37, null_frag, FP32, load, 4>;
+def MD  : BinaryRX <"md",  0x6C,   null_frag, FP64, load, 8>;
+
+// Extending multiplication (f32 x f32 -> f64).
+def MDER : BinaryRR<"mder", 0x3C, null_frag, FP64, FP32>;
+def MDE  : BinaryRX<"mde",  0x7C, null_frag, FP64, load, 4>;
+let isAsmParserOnly = 1 in {
+  def MER : BinaryRR<"mer", 0x3C, null_frag, FP64, FP32>;
+  def ME  : BinaryRX<"me",  0x7C, null_frag, FP64, load, 4>;
+}
+
+// Extending multiplication (f64 x f64 -> f128).
+def MXDR : BinaryRR<"mxdr", 0x27, null_frag, FP128, FP64>;
+def MXD  : BinaryRX<"mxd",  0x67, null_frag, FP128, load, 8>;
+
+// Fused multiply-add.
+def MAER : TernaryRRD<"maer", 0xB32E, null_frag, FP32, FP32>;
+def MADR : TernaryRRD<"madr", 0xB33E, null_frag, FP64, FP64>;
+def MAE  : TernaryRXF<"mae",  0xED2E, null_frag, FP32, FP32, load, 4>;
+def MAD  : TernaryRXF<"mad",  0xED3E, null_frag, FP64, FP64, load, 8>;
+
+// Fused multiply-subtract.
+def MSER : TernaryRRD<"mser", 0xB32F, null_frag, FP32, FP32>;
+def MSDR : TernaryRRD<"msdr", 0xB33F, null_frag, FP64, FP64>;
+def MSE  : TernaryRXF<"mse",  0xED2F, null_frag, FP32, FP32, load, 4>;
+def MSD  : TernaryRXF<"msd",  0xED3F, null_frag, FP64, FP64, load, 8>;
+
+// Multiplication (unnormalized).
+def MYR  : BinaryRRD<"myr",  0xB33B, null_frag, FP128, FP64>;
+def MYHR : BinaryRRD<"myhr", 0xB33D, null_frag, FP64,  FP64>;
+def MYLR : BinaryRRD<"mylr", 0xB339, null_frag, FP64,  FP64>;
+def MY   : BinaryRXF<"my",   0xED3B, null_frag, FP128, FP64, load, 8>;
+def MYH  : BinaryRXF<"myh",  0xED3D, null_frag, FP64,  FP64, load, 8>;
+def MYL  : BinaryRXF<"myl",  0xED39, null_frag, FP64,  FP64, load, 8>;
+
+// Fused multiply-add (unnormalized).
+def MAYR  : TernaryRRD<"mayr",  0xB33A, null_frag, FP128, FP64>;
+def MAYHR : TernaryRRD<"mayhr", 0xB33C, null_frag, FP64,  FP64>;
+def MAYLR : TernaryRRD<"maylr", 0xB338, null_frag, FP64,  FP64>;
+def MAY   : TernaryRXF<"may",   0xED3A, null_frag, FP128, FP64, load, 8>;
+def MAYH  : TernaryRXF<"mayh",  0xED3C, null_frag, FP64,  FP64, load, 8>;
+def MAYL  : TernaryRXF<"mayl",  0xED38, null_frag, FP64,  FP64, load, 8>;
+
+// Division.
+def DER : BinaryRR <"der", 0x3D,   null_frag, FP32,  FP32>;
+def DDR : BinaryRR <"ddr", 0x2D,   null_frag, FP64,  FP64>;
+def DXR : BinaryRRE<"dxr", 0xB22D, null_frag, FP128, FP128>;
+def DE  : BinaryRX <"de",  0x7D,   null_frag, FP32, load, 4>;
+def DD  : BinaryRX <"dd",  0x6D,   null_frag, FP64, load, 8>;
+
+
+//===----------------------------------------------------------------------===//
+// Comparisons
+//===----------------------------------------------------------------------===//
+
+let Defs = [CC] in {
+  def CER : CompareRR <"cer", 0x39,   null_frag, FP32,  FP32>;
+  def CDR : CompareRR <"cdr", 0x29,   null_frag, FP64,  FP64>;
+  def CXR : CompareRRE<"cxr", 0xB369, null_frag, FP128, FP128>;
+
+  def CE : CompareRX<"ce", 0x79, null_frag, FP32, load, 4>;
+  def CD : CompareRX<"cd", 0x69, null_frag, FP64, load, 8>;
+}
+
--- a/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ13.td
@ -908,6 +908,114 @@ def : InstRW<[FXa, Lat30, GroupAlone], (instregex "SFASR$")>;
 def : InstRW<[FXa, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
 def : InstRW<[FXb, Lat3, GroupAlone], (instregex "SRNM(B|T)?$")>;

+
+// --------------------- Hexadecimal floating point ------------------------- //
+
+//===----------------------------------------------------------------------===//
+// HFP: Move instructions
+//===----------------------------------------------------------------------===//
+
+// Load and Test
+def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)R$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Conversion instructions
+//===----------------------------------------------------------------------===//
+
+// Load rounded
+def : InstRW<[VecBF], (instregex "(LEDR|LRER)$")>;
+def : InstRW<[VecBF], (instregex "LEXR$")>;
+def : InstRW<[VecDF2, VecDF2], (instregex "(LDXR|LRDR)$")>;
+
+// Load lengthened
+def : InstRW<[LSU], (instregex "LDE$")>;
+def : InstRW<[FXb], (instregex "LDER$")>;
+def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "LX(D|E)$")>;
+def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "LX(D|E)R$")>;
+
+// Convert from fixed
+def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CE(F|G)R$")>;
+def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CD(F|G)R$")>;
+def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CX(F|G)R$")>;
+
+// Convert to fixed
+def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CF(E|D)R$")>;
+def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CG(E|D)R$")>;
+def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "C(F|G)XR$")>;
+
+// Convert BFP to HFP / HFP to BFP.
+def : InstRW<[VecBF], (instregex "THD(E)?R$")>;
+def : InstRW<[VecBF], (instregex "TB(E)?DR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Unary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Load Complement / Negative / Positive
+def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)DR$")>;
+def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)ER$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "L(C|N|P)XR$")>;
+
+// Halve
+def : InstRW<[VecBF], (instregex "H(E|D)R$")>;
+
+// Square root
+def : InstRW<[VecFPd, LSU], (instregex "SQ(E|D)$")>;
+def : InstRW<[VecFPd], (instregex "SQ(E|D)R$")>;
+def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "SQXR$")>;
+
+// Load FP integer
+def : InstRW<[VecBF], (instregex "FIER$")>;
+def : InstRW<[VecBF], (instregex "FIDR$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "FIXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Binary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Addition
+def : InstRW<[VecBF, LSU, Lat12], (instregex "A(E|D|U|W)$")>;
+def : InstRW<[VecBF], (instregex "A(E|D|U|W)R$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "AXR$")>;
+
+// Subtraction
+def : InstRW<[VecBF, LSU, Lat12], (instregex "S(E|D|U|W)$")>;
+def : InstRW<[VecBF], (instregex "S(E|D|U|W)R$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "SXR$")>;
+
+// Multiply
+def : InstRW<[VecBF, LSU, Lat12], (instregex "M(D|DE|E|EE)$")>;
+def : InstRW<[VecBF], (instregex "M(D|DE|E|EE)R$")>;
+def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MXD$")>;
+def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MXDR$")>;
+def : InstRW<[VecDF2, VecDF2, Lat20, GroupAlone], (instregex "MXR$")>;
+def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MY(H|L)?$")>;
+def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MY(H|L)?R$")>;
+
+// Multiply and add / subtract
+def : InstRW<[VecBF, LSU, Lat12, GroupAlone], (instregex "M(A|S)E$")>;
+def : InstRW<[VecBF, GroupAlone], (instregex "M(A|S)ER$")>;
+def : InstRW<[VecBF, LSU, Lat12, GroupAlone], (instregex "M(A|S)D$")>;
+def : InstRW<[VecBF], (instregex "M(A|S)DR$")>;
+def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MAY(H|L)?$")>;
+def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MAY(H|L)?R$")>;
+
+// Division
+def : InstRW<[VecFPd, LSU], (instregex "D(E|D)$")>;
+def : InstRW<[VecFPd], (instregex "D(E|D)R$")>;
+def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "DXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Comparisons
+//===----------------------------------------------------------------------===//
+
+// Compare
+def : InstRW<[VecXsPm, LSU, Lat8], (instregex "C(E|D)$")>;
+def : InstRW<[VecXsPm, Lat4], (instregex "C(E|D)R$")>;
+def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "CXR$")>;
+
+
 // --------------------------------- Vector --------------------------------- //

 //===----------------------------------------------------------------------===//
--- a/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ196.td
@ -839,5 +839,112 @@ def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
 def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
 def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;

+
+// --------------------- Hexadecimal floating point ------------------------- //
+
+//===----------------------------------------------------------------------===//
+// HFP: Move instructions
+//===----------------------------------------------------------------------===//
+
+// Load and Test
+def : InstRW<[FPU], (instregex "LT(D|E)R$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Conversion instructions
+//===----------------------------------------------------------------------===//
+
+// Load rounded
+def : InstRW<[FPU], (instregex "(LEDR|LRER)$")>;
+def : InstRW<[FPU], (instregex "LEXR$")>;
+def : InstRW<[FPU], (instregex "(LDXR|LRDR)$")>;
+
+// Load lengthened
+def : InstRW<[LSU], (instregex "LDE$")>;
+def : InstRW<[FXU], (instregex "LDER$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)R$")>;
+
+// Convert from fixed
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)R$")>;
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)R$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)R$")>;
+
+// Convert to fixed
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)R$")>;
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)R$")>;
+def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XR$")>;
+
+// Convert BFP to HFP / HFP to BFP.
+def : InstRW<[FPU], (instregex "THD(E)?R$")>;
+def : InstRW<[FPU], (instregex "TB(E)?DR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Unary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Load Complement / Negative / Positive
+def : InstRW<[FPU], (instregex "L(C|N|P)DR$")>;
+def : InstRW<[FPU], (instregex "L(C|N|P)ER$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XR$")>;
+
+// Halve
+def : InstRW<[FPU], (instregex "H(E|D)R$")>;
+
+// Square root
+def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)$")>;
+def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)R$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXR$")>;
+
+// Load FP integer
+def : InstRW<[FPU], (instregex "FIER$")>;
+def : InstRW<[FPU], (instregex "FIDR$")>;
+def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Binary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Addition
+def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D|U|W)$")>;
+def : InstRW<[FPU], (instregex "A(E|D|U|W)R$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXR$")>;
+
+// Subtraction
+def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D|U|W)$")>;
+def : InstRW<[FPU], (instregex "S(E|D|U|W)R$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXR$")>;
+
+// Multiply
+def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|E|EE)$")>;
+def : InstRW<[FPU], (instregex "M(D|DE|E|EE)R$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXD$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MY(H|L)?$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MY(H|L)?R$")>;
+
+// Multiply and add / subtract
+def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)E$")>;
+def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)ER$")>;
+def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)D$")>;
+def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat12, GroupAlone], (instregex "MAY(H|L)?$")>;
+def : InstRW<[FPU2, FPU2, GroupAlone], (instregex "MAY(H|L)?R$")>;
+
+// Division
+def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)$")>;
+def : InstRW<[FPU, Lat30], (instregex "D(E|D)R$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Comparisons
+//===----------------------------------------------------------------------===//
+
+// Compare
+def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)$")>;
+def : InstRW<[FPU], (instregex "C(E|D)R$")>;
+def : InstRW<[FPU, FPU, Lat15], (instregex "CXR$")>;
+
 }

--- a/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/lib/Target/SystemZ/SystemZScheduleZEC12.td
@ -877,5 +877,112 @@ def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
 def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
 def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;

+
+// --------------------- Hexadecimal floating point ------------------------- //
+
+//===----------------------------------------------------------------------===//
+// HFP: Move instructions
+//===----------------------------------------------------------------------===//
+
+// Load and Test
+def : InstRW<[FPU], (instregex "LT(D|E)R$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Conversion instructions
+//===----------------------------------------------------------------------===//
+
+// Load rounded
+def : InstRW<[FPU], (instregex "(LEDR|LRER)$")>;
+def : InstRW<[FPU], (instregex "LEXR$")>;
+def : InstRW<[FPU], (instregex "(LDXR|LRDR)$")>;
+
+// Load lengthened
+def : InstRW<[LSU], (instregex "LDE$")>;
+def : InstRW<[FXU], (instregex "LDER$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)R$")>;
+
+// Convert from fixed
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)R$")>;
+def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)R$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)R$")>;
+
+// Convert to fixed
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)R$")>;
+def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)R$")>;
+def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XR$")>;
+
+// Convert BFP to HFP / HFP to BFP.
+def : InstRW<[FPU], (instregex "THD(E)?R$")>;
+def : InstRW<[FPU], (instregex "TB(E)?DR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Unary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Load Complement / Negative / Positive
+def : InstRW<[FPU], (instregex "L(C|N|P)DR$")>;
+def : InstRW<[FPU], (instregex "L(C|N|P)ER$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XR$")>;
+
+// Halve
+def : InstRW<[FPU], (instregex "H(E|D)R$")>;
+
+// Square root
+def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)$")>;
+def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)R$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXR$")>;
+
+// Load FP integer
+def : InstRW<[FPU], (instregex "FIER$")>;
+def : InstRW<[FPU], (instregex "FIDR$")>;
+def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Binary arithmetic
+//===----------------------------------------------------------------------===//
+
+// Addition
+def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D|U|W)$")>;
+def : InstRW<[FPU], (instregex "A(E|D|U|W)R$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXR$")>;
+
+// Subtraction
+def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D|U|W)$")>;
+def : InstRW<[FPU], (instregex "S(E|D|U|W)R$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXR$")>;
+
+// Multiply
+def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|E|EE)$")>;
+def : InstRW<[FPU], (instregex "M(D|DE|E|EE)R$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXD$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MY(H|L)?$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MY(H|L)?R$")>;
+
+// Multiply and add / subtract
+def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)E$")>;
+def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)ER$")>;
+def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)D$")>;
+def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat12, GroupAlone], (instregex "MAY(H|L)?$")>;
+def : InstRW<[FPU2, FPU2, GroupAlone], (instregex "MAY(H|L)?R$")>;
+
+// Division
+def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)$")>;
+def : InstRW<[FPU, Lat30], (instregex "D(E|D)R$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXR$")>;
+
+//===----------------------------------------------------------------------===//
+// HFP: Comparisons
+//===----------------------------------------------------------------------===//
+
+// Compare
+def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)$")>;
+def : InstRW<[FPU], (instregex "C(E|D)R$")>;
+def : InstRW<[FPU, FPU, Lat15], (instregex "CXR$")>;
+
 }

--- a/test/MC/Disassembler/SystemZ/insns.txt
+++ b/test/MC/Disassembler/SystemZ/insns.txt
--- a/test/MC/SystemZ/insn-bad.s
+++ b/test/MC/SystemZ/insn-bad.s
@ -12,6 +12,14 @@
 	a	%r0, -1
 	a	%r0, 4096

+#CHECK: error: invalid operand
+#CHECK: ad	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: ad	%f0, 4096
+
+	ad	%f0, -1
+	ad	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: adb	%f0, -1
 #CHECK: error: invalid operand
@ -20,6 +28,14 @@
 	adb	%f0, -1
 	adb	%f0, 4096

+#CHECK: error: invalid operand
+#CHECK: ae	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: ae	%f0, 4096
+
+	ae	%f0, -1
+	ae	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: aeb	%f0, -1
 #CHECK: error: invalid operand
@ -328,6 +344,22 @@
 	asi	0, -129
 	asi	0, 128

+#CHECK: error: invalid operand
+#CHECK: au	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: au	%f0, 4096
+
+	au	%f0, -1
+	au	%f0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: aw	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: aw	%f0, 4096
+
+	aw	%f0, -1
+	aw	%f0, 4096
+
 #CHECK: error: invalid register pair
 #CHECK: axbr	%f0, %f2
 #CHECK: error: invalid register pair
@ -336,6 +368,13 @@
 	axbr	%f0, %f2
 	axbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: axr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: axr	%f2, %f0
+
+	axr	%f0, %f2
+	axr	%f2, %f0

 #CHECK: error: invalid operand
 #CHECK: ay	%r0, -524289
@ -612,6 +651,14 @@
 	c	%r0, -1
 	c	%r0, 4096

+#CHECK: error: invalid operand
+#CHECK: cd	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: cd	%f0, 4096
+
+	cd	%f0, -1
+	cd	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: cdb	%f0, -1
 #CHECK: error: invalid operand
@ -691,6 +738,14 @@
 	cdsy	%r0, %r0, 524288
 	cdsy	%r0, %r0, 0(%r1,%r2)

+#CHECK: error: invalid operand
+#CHECK: ce	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: ce	%f0, 4096
+
+	ce	%f0, -1
+	ce	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: ceb	%f0, -1
 #CHECK: error: invalid operand
@ -780,6 +835,17 @@

 	cfxbra	%r0, 0, %f0, 0

+#CHECK: error: invalid operand
+#CHECK: cfxr	%r0, -1, %f0
+#CHECK: error: invalid operand
+#CHECK: cfxr	%r0, 16, %f0
+#CHECK: error: invalid register pair
+#CHECK: cfxr	%r0, 0, %f2
+
+	cfxr	%r0, -1, %f0
+	cfxr	%r0, 16, %f0
+	cfxr	%r0, 0, %f2
+
 #CHECK: error: invalid operand
 #CHECK: cg	%r0, -524289
 #CHECK: error: invalid operand
@ -998,6 +1064,17 @@

 	cgxbra	%r0, 0, %f0, 0

+#CHECK: error: invalid operand
+#CHECK: cgxr	%r0, -1, %f0
+#CHECK: error: invalid operand
+#CHECK: cgxr	%r0, 16, %f0
+#CHECK: error: invalid register pair
+#CHECK: cgxr	%r0, 0, %f2
+
+	cgxr	%r0, -1, %f0
+	cgxr	%r0, 16, %f0
+	cgxr	%r0, 0, %f2
+
 #CHECK: error: invalid operand
 #CHECK: ch	%r0, -1
 #CHECK: error: invalid operand
@ -1966,6 +2043,11 @@

 	cxfbra	%f0, 0, %r0, 0

+#CHECK: error: invalid register pair
+#CHECK: cxfr	%f2, %r0
+
+	cxfr	%f2, %r0
+
 #CHECK: error: invalid register pair
 #CHECK: cxgbr	%f2, %r0

@ -1976,6 +2058,11 @@

 	cxgbra	%f0, 0, %r0, 0

+#CHECK: error: invalid register pair
+#CHECK: cxgr	%f2, %r0
+
+	cxgr	%f2, %r0
+
 #CHECK: error: instruction requires: fp-extension
 #CHECK: cxlfbr	%f0, 0, %r0, 0

@ -1986,6 +2073,14 @@

 	cxlgbr	%f0, 0, %r0, 0

+#CHECK: error: invalid register pair
+#CHECK: cxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: cxr	%f2, %f0
+
+	cxr	%f0, %f2
+	cxr	%f2, %f0
+
 #CHECK: error: invalid operand
 #CHECK: cy	%r0, -524289
 #CHECK: error: invalid operand
@ -2005,6 +2100,14 @@
 	d	%r0, 4096
 	d	%r1, 0

+#CHECK: error: invalid operand
+#CHECK: dd	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: dd	%f0, 4096
+
+	dd	%f0, -1
+	dd	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: ddb	%f0, -1
 #CHECK: error: invalid operand
@ -2013,6 +2116,14 @@
 	ddb	%f0, -1
 	ddb	%f0, 4096

+#CHECK: error: invalid operand
+#CHECK: de	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: de	%f0, 4096
+
+	de	%f0, -1
+	de	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: deb	%f0, -1
 #CHECK: error: invalid operand
@ -2167,6 +2278,14 @@
 	dxbr	%f0, %f2
 	dxbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: dxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: dxr	%f2, %f0
+
+	dxr	%f0, %f2
+	dxr	%f2, %f0
+
 #CHECK: error: invalid operand
 #CHECK: ecag	%r0, %r0, -524289
 #CHECK: error: invalid operand
@ -2336,6 +2455,14 @@

 	fixbra	%f0, 0, %f0, 0

+#CHECK: error: invalid register pair
+#CHECK: fixr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: fixr	%f2, %f0
+
+	fixr	%f0, %f2
+	fixr	%f2, %f0
+
 #CHECK: error: invalid register pair
 #CHECK: flogr	%r1, %r0

@ -2651,6 +2778,14 @@
 	lcxbr	%f0, %f2
 	lcxbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: lcxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: lcxr	%f2, %f0
+
+	lcxr	%f0, %f2
+	lcxr	%f2, %f0
+
 #CHECK: error: invalid operand
 #CHECK: ld	%f0, -1
 #CHECK: error: invalid operand
@ -2680,6 +2815,11 @@

 	ldxbra	%f0, 0, %f0, 0

+#CHECK: error: invalid register pair
+#CHECK: ldxr	%f0, %f2
+
+	ldxr	%f0, %f2
+
 #CHECK: error: invalid operand
 #CHECK: ldy	%f0, -524289
 #CHECK: error: invalid operand
@ -2714,6 +2854,11 @@

 	lexbra	%f0, 0, %f0, 0

+#CHECK: error: invalid register pair
+#CHECK: lexr	%f0, %f2
+
+	lexr	%f0, %f2
+
 #CHECK: error: invalid operand
 #CHECK: ley	%f0, -524289
 #CHECK: error: invalid operand
@ -3102,6 +3247,14 @@
 	lnxbr	%f0, %f2
 	lnxbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: lnxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: lnxr	%f2, %f0
+
+	lnxr	%f0, %f2
+	lnxr	%f2, %f0
+
 #CHECK: error: instruction requires: interlocked-access1
 #CHECK: lpd	%r0, 0, 0
 	lpd	%r0, 0, 0
@ -3129,6 +3282,19 @@
 	lpxbr	%f0, %f2
 	lpxbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: lpxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: lpxr	%f2, %f0
+
+	lpxr	%f0, %f2
+	lpxr	%f2, %f0
+
+#CHECK: error: invalid register pair
+#CHECK: lrdr	%f0, %f2
+
+	lrdr	%f0, %f2
+
 #CHECK: error: offset out of range
 #CHECK: lrl	%r0, -0x1000000002
 #CHECK: error: offset out of range
@ -3191,6 +3357,25 @@
 	ltxbr	%f0, %f14
 	ltxbr	%f14, %f0

+#CHECK: error: invalid register pair
+#CHECK: ltxr	%f0, %f14
+#CHECK: error: invalid register pair
+#CHECK: ltxr	%f14, %f0
+
+	ltxr	%f0, %f14
+	ltxr	%f14, %f0
+
+#CHECK: error: invalid operand
+#CHECK: lxd	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: lxd	%f0, 4096
+#CHECK: error: invalid register pair
+#CHECK: lxd	%f2, 0
+
+	lxd	%f0, -1
+	lxd	%f0, 4096
+	lxd	%f2, 0
+
 #CHECK: error: invalid operand
 #CHECK: lxdb	%f0, -1
 #CHECK: error: invalid operand
@ -3207,6 +3392,22 @@

 	lxdbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: lxdr	%f2, %f0
+
+	lxdr	%f2, %f0
+
+#CHECK: error: invalid operand
+#CHECK: lxe	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: lxe	%f0, 4096
+#CHECK: error: invalid register pair
+#CHECK: lxe	%f2, 0
+
+	lxe	%f0, -1
+	lxe	%f0, 4096
+	lxe	%f2, 0
+
 #CHECK: error: invalid operand
 #CHECK: lxeb	%f0, -1
 #CHECK: error: invalid operand
@ -3223,6 +3424,11 @@

 	lxebr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: lxer	%f2, %f0
+
+	lxer	%f2, %f0
+
 #CHECK: error: invalid register pair
 #CHECK: lxr	%f0, %f2
 #CHECK: error: invalid register pair
@ -3255,6 +3461,14 @@
 	m	%r0, 4096
 	m	%r1, 0

+#CHECK: error: invalid operand
+#CHECK: mad	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: mad	%f0, %f0, 4096
+
+	mad	%f0, %f0, -1
+	mad	%f0, %f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: madb	%f0, %f0, -1
 #CHECK: error: invalid operand
@ -3263,6 +3477,14 @@
 	madb	%f0, %f0, -1
 	madb	%f0, %f0, 4096

+#CHECK: error: invalid operand
+#CHECK: mae	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: mae	%f0, %f0, 4096
+
+	mae	%f0, %f0, -1
+	mae	%f0, %f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: maeb	%f0, %f0, -1
 #CHECK: error: invalid operand
@ -3271,6 +3493,38 @@
 	maeb	%f0, %f0, -1
 	maeb	%f0, %f0, 4096

+#CHECK: error: invalid operand
+#CHECK: may	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: may	%f0, %f0, 4096
+#CHECK: error: invalid register pair
+#CHECK: may	%f2, %f0, 0
+
+	may	%f0, %f0, -1
+	may	%f0, %f0, 4096
+	may	%f2, %f0, 0
+
+#CHECK: error: invalid operand
+#CHECK: mayh	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: mayh	%f0, %f0, 4096
+
+	mayh	%f0, %f0, -1
+	mayh	%f0, %f0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: mayl	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: mayl	%f0, %f0, 4096
+
+	mayl	%f0, %f0, -1
+	mayl	%f0, %f0, 4096
+
+#CHECK: error: invalid register pair
+#CHECK: mayr	%f2, %f0, %f0
+
+	mayr	%f2, %f0, %f0
+
 #CHECK: error: invalid operand
 #CHECK: mc	-1, 0
 #CHECK: error: invalid operand
@ -3288,6 +3542,14 @@
 	mc	0, -1
 	mc	0, 256

+#CHECK: error: invalid operand
+#CHECK: md	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: md	%f0, 4096
+
+	md	%f0, -1
+	md	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: mdb	%f0, -1
 #CHECK: error: invalid operand
@ -3296,6 +3558,14 @@
 	mdb	%f0, -1
 	mdb	%f0, 4096

+#CHECK: error: invalid operand
+#CHECK: mde	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: mde	%f0, 4096
+
+	mde	%f0, -1
+	mde	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: mdeb	%f0, -1
 #CHECK: error: invalid operand
@ -3304,6 +3574,22 @@
 	mdeb	%f0, -1
 	mdeb	%f0, 4096

+#CHECK: error: invalid operand
+#CHECK: me	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: me	%f0, 4096
+
+	me	%f0, -1
+	me	%f0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: mee	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: mee	%f0, 4096
+
+	mee	%f0, -1
+	mee	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: meeb	%f0, -1
 #CHECK: error: invalid operand
@ -3459,6 +3745,14 @@
 	ms	%r0, -1
 	ms	%r0, 4096

+#CHECK: error: invalid operand
+#CHECK: msd	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: msd	%f0, %f0, 4096
+
+	msd	%f0, %f0, -1
+	msd	%f0, %f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: msdb	%f0, %f0, -1
 #CHECK: error: invalid operand
@ -3467,6 +3761,14 @@
 	msdb	%f0, %f0, -1
 	msdb	%f0, %f0, 4096

+#CHECK: error: invalid operand
+#CHECK: mse	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: mse	%f0, %f0, 4096
+
+	mse	%f0, %f0, -1
+	mse	%f0, %f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: mseb	%f0, %f0, -1
 #CHECK: error: invalid operand
@ -3902,6 +4204,17 @@
 	mxbr	%f0, %f2
 	mxbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: mxd	%f2, 0
+#CHECK: error: invalid operand
+#CHECK: mxd	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: mxd	%f0, 4096
+
+	mxd	%f2, 0
+	mxd	%f0, -1
+	mxd	%f0, 4096
+
 #CHECK: error: invalid register pair
 #CHECK: mxdb	%f2, 0
 #CHECK: error: invalid operand
@ -3918,6 +4231,51 @@

 	mxdbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: mxdr	%f2, %f0
+
+	mxdr	%f2, %f0
+
+#CHECK: error: invalid register pair
+#CHECK: mxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: mxr	%f2, %f0
+
+	mxr	%f0, %f2
+	mxr	%f2, %f0
+
+#CHECK: error: invalid operand
+#CHECK: my	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: my	%f0, %f0, 4096
+#CHECK: error: invalid register pair
+#CHECK: my	%f2, %f0, 0
+
+	my	%f0, %f0, -1
+	my	%f0, %f0, 4096
+	my	%f2, %f0, 0
+
+#CHECK: error: invalid operand
+#CHECK: myh	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: myh	%f0, %f0, 4096
+
+	myh	%f0, %f0, -1
+	myh	%f0, %f0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: myl	%f0, %f0, -1
+#CHECK: error: invalid operand
+#CHECK: myl	%f0, %f0, 4096
+
+	myl	%f0, %f0, -1
+	myl	%f0, %f0, 4096
+
+#CHECK: error: invalid register pair
+#CHECK: myr	%f2, %f0, %f0
+
+	myr	%f2, %f0, %f0
+
 #CHECK: error: invalid operand
 #CHECK: n	%r0, -1
 #CHECK: error: invalid operand
@ -4570,6 +4928,14 @@
 	s	%r0, -1
 	s	%r0, 4096

+#CHECK: error: invalid operand
+#CHECK: sd	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: sd	%f0, 4096
+
+	sd	%f0, -1
+	sd	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: sdb	%f0, -1
 #CHECK: error: invalid operand
@ -4578,6 +4944,14 @@
 	sdb	%f0, -1
 	sdb	%f0, 4096

+#CHECK: error: invalid operand
+#CHECK: se	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: se	%f0, 4096
+
+	se	%f0, -1
+	se	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: seb	%f0, -1
 #CHECK: error: invalid operand
@ -4850,6 +5224,14 @@
 	sp	0(1,%r2), 0(%r1,%r2)
 	sp	0(-), 0(1)

+#CHECK: error: invalid operand
+#CHECK: sqd	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: sqd	%f0, 4096
+
+	sqd	%f0, -1
+	sqd	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: sqdb	%f0, -1
 #CHECK: error: invalid operand
@ -4858,6 +5240,14 @@
 	sqdb	%f0, -1
 	sqdb	%f0, 4096

+#CHECK: error: invalid operand
+#CHECK: sqe	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: sqe	%f0, 4096
+
+	sqe	%f0, -1
+	sqe	%f0, 4096
+
 #CHECK: error: invalid operand
 #CHECK: sqeb	%f0, -1
 #CHECK: error: invalid operand
@ -4874,6 +5264,14 @@
 	sqxbr	%f0, %f2
 	sqxbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: sqxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: sqxr	%f2, %f0
+
+	sqxr	%f0, %f2
+	sqxr	%f2, %f0
+
 #CHECK: error: invalid operand
 #CHECK: sra	%r0,-1
 #CHECK: error: invalid operand
@ -5358,6 +5756,22 @@
 	sty	%r0, -524289
 	sty	%r0, 524288

+#CHECK: error: invalid operand
+#CHECK: su	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: su	%f0, 4096
+
+	su	%f0, -1
+	su	%f0, 4096
+
+#CHECK: error: invalid operand
+#CHECK: sw	%f0, -1
+#CHECK: error: invalid operand
+#CHECK: sw	%f0, 4096
+
+	sw	%f0, -1
+	sw	%f0, 4096
+
 #CHECK: error: invalid register pair
 #CHECK: sxbr	%f0, %f2
 #CHECK: error: invalid register pair
@ -5366,6 +5780,14 @@
 	sxbr	%f0, %f2
 	sxbr	%f2, %f0

+#CHECK: error: invalid register pair
+#CHECK: sxr	%f0, %f2
+#CHECK: error: invalid register pair
+#CHECK: sxr	%f2, %f0
+
+	sxr	%f0, %f2
+	sxr	%f2, %f0
+
 #CHECK: error: invalid operand
 #CHECK: sy	%r0, -524289
 #CHECK: error: invalid operand
@ -5374,6 +5796,22 @@
 	sy	%r0, -524289
 	sy	%r0, 524288

+#CHECK: error: invalid operand
+#CHECK: tbdr	%f0, -1, %f0
+#CHECK: error: invalid operand
+#CHECK: tbdr	%f0, 16, %f0
+
+	tbdr	%f0, -1, %f0
+	tbdr	%f0, 16, %f0
+
+#CHECK: error: invalid operand
+#CHECK: tbedr	%f0, -1, %f0
+#CHECK: error: invalid operand
+#CHECK: tbedr	%f0, 16, %f0
+
+	tbedr	%f0, -1, %f0
+	tbedr	%f0, 16, %f0
+
 #CHECK: error: invalid operand
 #CHECK: tcdb	%f0, -1
 #CHECK: error: invalid operand
--- a/test/MC/SystemZ/insn-good.s
+++ b/test/MC/SystemZ/insn-good.s