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[DAG] Introduce peekThroughBitcast function. NFCI.

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llvm-svn: 310405
This commit is contained in:
Nirav Dave 2017-08-08 20:01:18 +00:00
parent 7c73b3138e
commit c7aeeaea2c
1 changed files with 14 additions and 23 deletions
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37
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -12419,6 +12419,12 @@ bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode,
return false;
}
static SDValue peekThroughBitcast(SDValue V) {
while (V.getOpcode() == ISD::BITCAST)
V = V.getOperand(0);
return V;
}
SDValue DAGCombiner::getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
unsigned NumStores) {
SmallVector<SDValue, 8> Chains;
@ -14614,8 +14620,7 @@ static SDValue combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) {
for (SDValue Op : N->ops()) {
// Peek through any bitcast.
while (Op.getOpcode() == ISD::BITCAST)
Op = Op.getOperand(0);
Op = peekThroughBitcast(Op);
// UNDEF nodes convert to UNDEF shuffle mask values.
if (Op.isUndef()) {
@ -14634,8 +14639,7 @@ static SDValue combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) {
EVT ExtVT = ExtVec.getValueType();
// Peek through any bitcast.
while (ExtVec.getOpcode() == ISD::BITCAST)
ExtVec = ExtVec.getOperand(0);
ExtVec = peekThroughBitcast(ExtVec);
// UNDEF nodes convert to UNDEF shuffle mask values.
if (ExtVec.isUndef()) {
@ -14860,9 +14864,7 @@ static SDValue narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG) {
// We are looking for an optionally bitcasted wide vector binary operator
// feeding an extract subvector.
SDValue BinOp = Extract->getOperand(0);
if (BinOp.getOpcode() == ISD::BITCAST)
BinOp = BinOp.getOperand(0);
SDValue BinOp = peekThroughBitcast(Extract->getOperand(0));
// TODO: The motivating case for this transform is an x86 AVX1 target. That
// target has temptingly almost legal versions of bitwise logic ops in 256-bit
@ -14886,13 +14888,8 @@ static SDValue narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG) {
return SDValue();
// Peek through bitcasts of the binary operator operands if needed.
SDValue LHS = BinOp.getOperand(0);
if (LHS.getOpcode() == ISD::BITCAST)
LHS = LHS.getOperand(0);
SDValue RHS = BinOp.getOperand(1);
if (RHS.getOpcode() == ISD::BITCAST)
RHS = RHS.getOperand(0);
SDValue LHS = peekThroughBitcast(BinOp.getOperand(0));
SDValue RHS = peekThroughBitcast(BinOp.getOperand(1));
// We need at least one concatenation operation of a binop operand to make
// this transform worthwhile. The concat must double the input vector sizes.
@ -14991,8 +14988,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
}
// Skip bitcasting
if (V->getOpcode() == ISD::BITCAST)
V = V.getOperand(0);
V = peekThroughBitcast(V);
if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
// Handle only simple case where vector being inserted and vector
@ -15349,9 +15345,7 @@ static SDValue combineTruncationShuffle(ShuffleVectorSDNode *SVN,
if (!VT.isInteger() || IsBigEndian)
return SDValue();
SDValue N0 = SVN->getOperand(0);
while (N0.getOpcode() == ISD::BITCAST)
N0 = N0.getOperand(0);
SDValue N0 = peekThroughBitcast(SVN->getOperand(0));
unsigned Opcode = N0.getOpcode();
if (Opcode != ISD::ANY_EXTEND_VECTOR_INREG &&
@ -15937,7 +15931,7 @@ SDValue DAGCombiner::visitFP16_TO_FP(SDNode *N) {
SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
EVT VT = N->getValueType(0);
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue RHS = peekThroughBitcast(N->getOperand(1));
SDLoc DL(N);
// Make sure we're not running after operation legalization where it
@ -15948,9 +15942,6 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
if (N->getOpcode() != ISD::AND)
return SDValue();
if (RHS.getOpcode() == ISD::BITCAST)
RHS = RHS.getOperand(0);
if (RHS.getOpcode() != ISD::BUILD_VECTOR)
return SDValue();