From c7baa2832f6b070305b5f9e8465eb06bd236e5aa Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Wed, 7 Oct 2009 23:47:21 +0000 Subject: [PATCH] Convert more NEON tests to use FileCheck. llvm-svn: 83507 --- test/CodeGen/ARM/vmov.ll | 48 +++++++++++++++++++++++++++++++++------ test/CodeGen/ARM/vmovl.ll | 20 ++++++++++------ test/CodeGen/ARM/vmovn.ll | 11 +++++---- test/CodeGen/ARM/vmul.ll | 27 +++++++++++++++++----- test/CodeGen/ARM/vmull.ll | 23 ++++++++++++------- test/CodeGen/ARM/vmvn.ll | 20 +++++++++++++--- 6 files changed, 114 insertions(+), 35 deletions(-) diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index c4cb2044df5..f43266cf852 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -1,101 +1,135 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep vmov.i8 %t | count 2 -; RUN: grep vmov.i16 %t | count 4 -; RUN: grep vmov.i32 %t | count 12 -; RUN: grep vmov.i64 %t | count 2 -; Note: function names do not include "vmov" to allow simple grep for opcodes +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @v_movi8() nounwind { +;CHECK: v_movi8: +;CHECK: vmov.i8 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <4 x i16> @v_movi16a() nounwind { +;CHECK: v_movi16a: +;CHECK: vmov.i16 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > } ; 0x1000 = 4096 define <4 x i16> @v_movi16b() nounwind { +;CHECK: v_movi16b: +;CHECK: vmov.i16 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > } define <2 x i32> @v_movi32a() nounwind { +;CHECK: v_movi32a: +;CHECK: vmov.i32 ret <2 x i32> < i32 32, i32 32 > } ; 0x2000 = 8192 define <2 x i32> @v_movi32b() nounwind { +;CHECK: v_movi32b: +;CHECK: vmov.i32 ret <2 x i32> < i32 8192, i32 8192 > } ; 0x200000 = 2097152 define <2 x i32> @v_movi32c() nounwind { +;CHECK: v_movi32c: +;CHECK: vmov.i32 ret <2 x i32> < i32 2097152, i32 2097152 > } ; 0x20000000 = 536870912 define <2 x i32> @v_movi32d() nounwind { +;CHECK: v_movi32d: +;CHECK: vmov.i32 ret <2 x i32> < i32 536870912, i32 536870912 > } ; 0x20ff = 8447 define <2 x i32> @v_movi32e() nounwind { +;CHECK: v_movi32e: +;CHECK: vmov.i32 ret <2 x i32> < i32 8447, i32 8447 > } ; 0x20ffff = 2162687 define <2 x i32> @v_movi32f() nounwind { +;CHECK: v_movi32f: +;CHECK: vmov.i32 ret <2 x i32> < i32 2162687, i32 2162687 > } ; 0xff0000ff0000ffff = 18374687574888349695 define <1 x i64> @v_movi64() nounwind { +;CHECK: v_movi64: +;CHECK: vmov.i64 ret <1 x i64> < i64 18374687574888349695 > } define <16 x i8> @v_movQi8() nounwind { +;CHECK: v_movQi8: +;CHECK: vmov.i8 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <8 x i16> @v_movQi16a() nounwind { +;CHECK: v_movQi16a: +;CHECK: vmov.i16 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > } ; 0x1000 = 4096 define <8 x i16> @v_movQi16b() nounwind { +;CHECK: v_movQi16b: +;CHECK: vmov.i16 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > } define <4 x i32> @v_movQi32a() nounwind { +;CHECK: v_movQi32a: +;CHECK: vmov.i32 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > } ; 0x2000 = 8192 define <4 x i32> @v_movQi32b() nounwind { +;CHECK: v_movQi32b: +;CHECK: vmov.i32 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > } ; 0x200000 = 2097152 define <4 x i32> @v_movQi32c() nounwind { +;CHECK: v_movQi32c: +;CHECK: vmov.i32 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > } ; 0x20000000 = 536870912 define <4 x i32> @v_movQi32d() nounwind { +;CHECK: v_movQi32d: +;CHECK: vmov.i32 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > } ; 0x20ff = 8447 define <4 x i32> @v_movQi32e() nounwind { +;CHECK: v_movQi32e: +;CHECK: vmov.i32 ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > } ; 0x20ffff = 2162687 define <4 x i32> @v_movQi32f() nounwind { +;CHECK: v_movQi32f: +;CHECK: vmov.i32 ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > } ; 0xff0000ff0000ffff = 18374687574888349695 define <2 x i64> @v_movQi64() nounwind { +;CHECK: v_movQi64: +;CHECK: vmov.i64 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > } - diff --git a/test/CodeGen/ARM/vmovl.ll b/test/CodeGen/ARM/vmovl.ll index 47576806273..beb16130ef5 100644 --- a/test/CodeGen/ARM/vmovl.ll +++ b/test/CodeGen/ARM/vmovl.ll @@ -1,42 +1,48 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vmovl\\.s8} %t | count 1 -; RUN: grep {vmovl\\.s16} %t | count 1 -; RUN: grep {vmovl\\.s32} %t | count 1 -; RUN: grep {vmovl\\.u8} %t | count 1 -; RUN: grep {vmovl\\.u16} %t | count 1 -; RUN: grep {vmovl\\.u32} %t | count 1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { +;CHECK: vmovls8: +;CHECK: vmovl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8> %tmp1) ret <8 x i16> %tmp2 } define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { +;CHECK: vmovls16: +;CHECK: vmovl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %tmp1) ret <4 x i32> %tmp2 } define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { +;CHECK: vmovls32: +;CHECK: vmovl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32> %tmp1) ret <2 x i64> %tmp2 } define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { +;CHECK: vmovlu8: +;CHECK: vmovl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8> %tmp1) ret <8 x i16> %tmp2 } define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { +;CHECK: vmovlu16: +;CHECK: vmovl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16> %tmp1) ret <4 x i32> %tmp2 } define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { +;CHECK: vmovlu32: +;CHECK: vmovl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32> %tmp1) ret <2 x i64> %tmp2 diff --git a/test/CodeGen/ARM/vmovn.ll b/test/CodeGen/ARM/vmovn.ll index 173bb52e31c..7bf049fa9d4 100644 --- a/test/CodeGen/ARM/vmovn.ll +++ b/test/CodeGen/ARM/vmovn.ll @@ -1,21 +1,24 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vmovn\\.i16} %t | count 1 -; RUN: grep {vmovn\\.i32} %t | count 1 -; RUN: grep {vmovn\\.i64} %t | count 1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { +;CHECK: vmovni16: +;CHECK: vmovn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16> %tmp1) ret <8 x i8> %tmp2 } define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { +;CHECK: vmovni32: +;CHECK: vmovn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32> %tmp1) ret <4 x i16> %tmp2 } define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { +;CHECK: vmovni64: +;CHECK: vmovn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64> %tmp1) ret <2 x i32> %tmp2 diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 38abcca9a38..83ec55e91bc 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -1,11 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vmul\\.i8} %t | count 2 -; RUN: grep {vmul\\.i16} %t | count 2 -; RUN: grep {vmul\\.i32} %t | count 2 -; RUN: grep {vmul\\.f32} %t | count 2 -; RUN: grep {vmul\\.p8} %t | count 2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vmuli8: +;CHECK: vmul.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = mul <8 x i8> %tmp1, %tmp2 @@ -13,6 +10,8 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vmuli16: +;CHECK: vmul.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = mul <4 x i16> %tmp1, %tmp2 @@ -20,6 +19,8 @@ define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vmuli32: +;CHECK: vmul.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = mul <2 x i32> %tmp1, %tmp2 @@ -27,6 +28,8 @@ define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { +;CHECK: vmulf32: +;CHECK: vmul.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B %tmp3 = mul <2 x float> %tmp1, %tmp2 @@ -34,6 +37,8 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vmulp8: +;CHECK: vmul.p8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -41,6 +46,8 @@ define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: vmulQi8: +;CHECK: vmul.i8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = mul <16 x i8> %tmp1, %tmp2 @@ -48,6 +55,8 @@ define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { +;CHECK: vmulQi16: +;CHECK: vmul.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B %tmp3 = mul <8 x i16> %tmp1, %tmp2 @@ -55,6 +64,8 @@ define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +;CHECK: vmulQi32: +;CHECK: vmul.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B %tmp3 = mul <4 x i32> %tmp1, %tmp2 @@ -62,6 +73,8 @@ define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { +;CHECK: vmulQf32: +;CHECK: vmul.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B %tmp3 = mul <4 x float> %tmp1, %tmp2 @@ -69,6 +82,8 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: vmulQp8: +;CHECK: vmul.p8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) diff --git a/test/CodeGen/ARM/vmull.ll b/test/CodeGen/ARM/vmull.ll index c3bd141d60c..56149dac30d 100644 --- a/test/CodeGen/ARM/vmull.ll +++ b/test/CodeGen/ARM/vmull.ll @@ -1,13 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vmull\\.s8} %t | count 1 -; RUN: grep {vmull\\.s16} %t | count 1 -; RUN: grep {vmull\\.s32} %t | count 1 -; RUN: grep {vmull\\.u8} %t | count 1 -; RUN: grep {vmull\\.u16} %t | count 1 -; RUN: grep {vmull\\.u32} %t | count 1 -; RUN: grep {vmull\\.p8} %t | count 1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vmulls8: +;CHECK: vmull.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -15,6 +10,8 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vmulls16: +;CHECK: vmull.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -22,6 +19,8 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vmulls32: +;CHECK: vmull.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -29,6 +28,8 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vmullu8: +;CHECK: vmull.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -36,6 +37,8 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vmullu16: +;CHECK: vmull.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -43,6 +46,8 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vmullu32: +;CHECK: vmull.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -50,6 +55,8 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vmullp8: +;CHECK: vmull.p8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) diff --git a/test/CodeGen/ARM/vmvn.ll b/test/CodeGen/ARM/vmvn.ll index f71777b9b80..d756b768bbe 100644 --- a/test/CodeGen/ARM/vmvn.ll +++ b/test/CodeGen/ARM/vmvn.ll @@ -1,50 +1,64 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep vmvn %t | count 8 -; Note: function names do not include "vmvn" to allow simple grep for opcodes +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { +;CHECK: v_mvni8: +;CHECK: vmvn %tmp1 = load <8 x i8>* %A %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > ret <8 x i8> %tmp2 } define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { +;CHECK: v_mvni16: +;CHECK: vmvn %tmp1 = load <4 x i16>* %A %tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 > ret <4 x i16> %tmp2 } define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { +;CHECK: v_mvni32: +;CHECK: vmvn %tmp1 = load <2 x i32>* %A %tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 > ret <2 x i32> %tmp2 } define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { +;CHECK: v_mvni64: +;CHECK: vmvn %tmp1 = load <1 x i64>* %A %tmp2 = xor <1 x i64> %tmp1, < i64 -1 > ret <1 x i64> %tmp2 } define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { +;CHECK: v_mvnQi8: +;CHECK: vmvn %tmp1 = load <16 x i8>* %A %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > ret <16 x i8> %tmp2 } define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { +;CHECK: v_mvnQi16: +;CHECK: vmvn %tmp1 = load <8 x i16>* %A %tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > ret <8 x i16> %tmp2 } define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { +;CHECK: v_mvnQi32: +;CHECK: vmvn %tmp1 = load <4 x i32>* %A %tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 > ret <4 x i32> %tmp2 } define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { +;CHECK: v_mvnQi64: +;CHECK: vmvn %tmp1 = load <2 x i64>* %A %tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 > ret <2 x i64> %tmp2