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[PowerPC] Support extended mnemonics mffprwz etc.
Summary: Reported in https://github.com/opencv/opencv/issues/15413. We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions eg: mffprd,mtfprd etc. We only support one of them, this patch add the others. Reviewers: nemanjai, steven.zhang, hfinkel, #powerpc Reviewed By: hfinkel Subscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66963 llvm-svn: 370411
This commit is contained in:
Jinsong Ji
parent
6017c1a2f3
commit
c7cbe2ad6b
@ -125,8 +125,8 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
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(instregex "SRAD(I)?$"),
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(instregex "EXTSWSLI_32_64$"),
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(instregex "MFV(S)?RD$"),
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(instregex "MTVSRD$"),
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(instregex "MTVSRW(A|Z)$"),
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(instregex "MTV(S)?RD$"),
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(instregex "MTV(S)?RW(A|Z)$"),
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(instregex "CMP(WI|LWI|W|LW)(8)?$"),
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(instregex "CMP(L)?D(I)?$"),
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(instregex "SUBF(I)?C(8)?$"),
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@ -159,6 +159,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
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XSNEGDP,
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XSCPSGNDP,
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MFVSRWZ,
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MFVRWZ,
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EXTSWSLI,
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SRADI_32,
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RLDIC,
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@ -1593,16 +1593,33 @@ let Predicates = [HasDirectMove] in {
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def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
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"mfvsrwz $rA, $XT", IIC_VecGeneral,
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[(set i32:$rA, (PPCmfvsr f64:$XT))]>;
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let isCodeGenOnly = 1 in
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def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
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"mfvsrwz $rA, $XT", IIC_VecGeneral,
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[]>;
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def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
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"mtvsrd $XT, $rA", IIC_VecGeneral,
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[(set f64:$XT, (PPCmtvsra i64:$rA))]>,
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Requires<[In64BitMode]>;
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let isCodeGenOnly = 1 in
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def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA),
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"mtvsrd $XT, $rA", IIC_VecGeneral,
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[]>,
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Requires<[In64BitMode]>;
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def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
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"mtvsrwa $XT, $rA", IIC_VecGeneral,
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[(set f64:$XT, (PPCmtvsra i32:$rA))]>;
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let isCodeGenOnly = 1 in
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def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA),
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"mtvsrwa $XT, $rA", IIC_VecGeneral,
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[]>;
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def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
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"mtvsrwz $XT, $rA", IIC_VecGeneral,
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[(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
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let isCodeGenOnly = 1 in
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def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA),
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"mtvsrwz $XT, $rA", IIC_VecGeneral,
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[]>;
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} // HasDirectMove
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let Predicates = [IsISA3_0, HasDirectMove] in {
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@ -1626,6 +1643,22 @@ def : InstAlias<"mfvrd $rA, $XT",
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(MFVRD g8rc:$rA, vrrc:$XT), 0>;
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def : InstAlias<"mffprd $rA, $src",
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(MFVSRD g8rc:$rA, f8rc:$src)>;
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def : InstAlias<"mtvrd $XT, $rA",
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(MTVRD vrrc:$XT, g8rc:$rA), 0>;
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def : InstAlias<"mtfprd $dst, $rA",
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(MTVSRD f8rc:$dst, g8rc:$rA)>;
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def : InstAlias<"mfvrwz $rA, $XT",
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(MFVRWZ gprc:$rA, vrrc:$XT), 0>;
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def : InstAlias<"mffprwz $rA, $src",
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(MFVSRWZ gprc:$rA, f8rc:$src)>;
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def : InstAlias<"mtvrwa $XT, $rA",
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(MTVRWA vrrc:$XT, gprc:$rA), 0>;
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def : InstAlias<"mtfprwa $dst, $rA",
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(MTVSRWA f8rc:$dst, gprc:$rA)>;
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def : InstAlias<"mtvrwz $XT, $rA",
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(MTVRWZ vrrc:$XT, gprc:$rA), 0>;
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def : InstAlias<"mtfprwz $dst, $rA",
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(MTVSRWZ f8rc:$dst, gprc:$rA)>;
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/* Direct moves of various widths from GPR's into VSR's. Each move lines
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the value up into element 0 (both BE and LE). Namely, entities smaller than
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@ -40,7 +40,7 @@ entry:
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ret double %0
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; CHECK-P7: std 3,
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; CHECK-P7: lfd 1,
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; CHECK: mtvsrd 1, 3
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; CHECK: mtfprd 1, 3
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}
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define zeroext i32 @f32toi32u(float %a) {
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@ -80,5 +80,5 @@ entry:
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ret double %0
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; CHECK-P7: std 3,
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; CHECK-P7: lfd 1,
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; CHECK: mtvsrd 1, 3
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; CHECK: mtfprd 1, 3
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}
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@ -112,7 +112,7 @@ entry:
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%2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
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ret fp128 %2
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; CHECK-LABEL: insert_exp_qp
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; CHECK-DAG: mtvsrd [[FPREG:f[0-9]+]], r3
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; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3
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; CHECK-DAG: lxvx [[VECREG:v[0-9]+]]
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; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
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; CHECK: blr
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@ -69,7 +69,7 @@ entry:
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store i32 %add, i32* %arrayidx6, align 4, !tbaa !1
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ret void
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; CHECK: mtvsrwa
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; CHECK: mtfprwa
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; CHECK: blr
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}
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@ -25,7 +25,7 @@ entry:
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define float @_Z6testfcc(i8 zeroext %arg) {
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; CHECK-LABEL: _Z6testfcc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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@ -58,7 +58,7 @@ entry:
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define double @_Z6testdcc(i8 zeroext %arg) {
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; CHECK-LABEL: _Z6testdcc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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@ -91,7 +91,7 @@ entry:
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define float @_Z7testfuch(i8 zeroext %arg) {
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; CHECK-LABEL: _Z7testfuch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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@ -124,7 +124,7 @@ entry:
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define double @_Z7testduch(i8 zeroext %arg) {
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; CHECK-LABEL: _Z7testduch:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stb r3, -1(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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@ -142,7 +142,7 @@ define signext i16 @_Z6testsff(float %arg) {
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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@ -157,7 +157,7 @@ entry:
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define float @_Z6testfss(i16 signext %arg) {
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; CHECK-LABEL: _Z6testfss:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwa f0, r3
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: blr
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@ -175,7 +175,7 @@ define signext i16 @_Z6testsdd(double %arg) {
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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@ -190,7 +190,7 @@ entry:
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define double @_Z6testdss(i16 signext %arg) {
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; CHECK-LABEL: _Z6testdss:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwa f0, r3
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvsxddp f1, f0
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; CHECK-NEXT: blr
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@ -223,7 +223,7 @@ entry:
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define float @_Z7testfust(i16 zeroext %arg) {
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; CHECK-LABEL: _Z7testfust:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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@ -256,7 +256,7 @@ entry:
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define double @_Z7testdust(i16 zeroext %arg) {
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; CHECK-LABEL: _Z7testdust:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: sth r3, -2(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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@ -274,7 +274,7 @@ define signext i32 @_Z6testiff(float %arg) {
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfs f1, -4(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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@ -289,7 +289,7 @@ entry:
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define float @_Z6testfii(i32 signext %arg) {
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; CHECK-LABEL: _Z6testfii:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwa f0, r3
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: blr
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@ -307,7 +307,7 @@ define signext i32 @_Z6testidd(double %arg) {
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws f0, f1
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; CHECK-NEXT: stfd f1, -8(r1)
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; CHECK-NEXT: mfvsrwz r3, f0
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; CHECK-NEXT: mffprwz r3, f0
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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@ -322,7 +322,7 @@ entry:
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define double @_Z6testdii(i32 signext %arg) {
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; CHECK-LABEL: _Z6testdii:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwa f0, r3
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; CHECK-NEXT: mtfprwa f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvsxddp f1, f0
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; CHECK-NEXT: blr
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@ -355,7 +355,7 @@ entry:
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define float @_Z7testfuij(i32 zeroext %arg) {
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; CHECK-LABEL: _Z7testfuij:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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@ -388,7 +388,7 @@ entry:
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define double @_Z7testduij(i32 zeroext %arg) {
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; CHECK-LABEL: _Z7testduij:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwz f0, r3
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; CHECK-NEXT: mtfprwz f0, r3
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; CHECK-NEXT: stw r3, -4(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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@ -420,7 +420,7 @@ entry:
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define float @_Z7testfllx(i64 %arg) {
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; CHECK-LABEL: _Z7testfllx:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrd f0, r3
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: blr
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@ -452,7 +452,7 @@ entry:
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define double @_Z7testdllx(i64 %arg) {
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; CHECK-LABEL: _Z7testdllx:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrd f0, r3
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: xscvsxddp f1, f0
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; CHECK-NEXT: blr
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@ -484,7 +484,7 @@ entry:
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define float @_Z8testfully(i64 %arg) {
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; CHECK-LABEL: _Z8testfully:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrd f0, r3
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: xscvuxdsp f1, f0
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; CHECK-NEXT: blr
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@ -516,7 +516,7 @@ entry:
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define double @_Z8testdully(i64 %arg) {
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; CHECK-LABEL: _Z8testdully:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrd f0, r3
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: xscvuxddp f1, f0
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; CHECK-NEXT: blr
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@ -6,7 +6,7 @@ define i1 @Test(double %a) {
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; CHECK-LABEL: Test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvdpsxws 0, 1
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; CHECK-NEXT: mfvsrwz 3, 0
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: xori 3, 3, 65534
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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@ -17,7 +17,7 @@ if.end: ; preds = %if.then, %entry
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; CHECK: @foo
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; CHECK: mr [[NEWREG:[0-9]+]], 3
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; CHECK: mr [[REG1:[0-9]+]], 4
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; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4
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; CHECK: mtfprd [[NEWREG2:[0-9]+]], 4
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; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]
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; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]
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; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]
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72
test/CodeGen/PowerPC/inlineasm-extendedmne.ll
Normal file
72
test/CodeGen/PowerPC/inlineasm-extendedmne.ll
Normal file
@ -0,0 +1,72 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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define dso_local void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mfvsrd r0, vs33
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mffprd r0, f3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mfvsrd r0, vs34
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mfvsrwz r0, vs33
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mffprwz r0, f3
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mfvsrwz r0, vs34
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mtvsrd vs33, r0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mtfprd f3, r0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: mtvsrd vs34, r0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
|
||||
; CHECK-NEXT: mtvsrwa vs33, r0
|
||||
; CHECK-NEXT: #NO_APP
|
||||
; CHECK-NEXT: #APP
|
||||
; CHECK-NEXT: mtfprwa f3, r0
|
||||
; CHECK-NEXT: #NO_APP
|
||||
; CHECK-NEXT: #APP
|
||||
; CHECK-NEXT: mtvsrwa vs34, r0
|
||||
; CHECK-NEXT: #NO_APP
|
||||
; CHECK-NEXT: #APP
|
||||
; CHECK-NEXT: mtvsrwz vs33, r0
|
||||
; CHECK-NEXT: #NO_APP
|
||||
; CHECK-NEXT: #APP
|
||||
; CHECK-NEXT: mtfprwz f3, r0
|
||||
; CHECK-NEXT: #NO_APP
|
||||
; CHECK-NEXT: #APP
|
||||
; CHECK-NEXT: mtvsrwz vs34, r0
|
||||
; CHECK-NEXT: #NO_APP
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
call void asm sideeffect "mfvsrd 0,33", ""()
|
||||
call void asm sideeffect "mffprd 0,3", ""()
|
||||
call void asm sideeffect "mfvrd 0,2", ""()
|
||||
call void asm sideeffect "mfvsrwz 0,33", ""()
|
||||
call void asm sideeffect "mffprwz 0,3", ""()
|
||||
call void asm sideeffect "mfvrwz 0,2", ""()
|
||||
call void asm sideeffect "mtvsrd 33,0", ""()
|
||||
call void asm sideeffect "mtfprd 3,0", ""()
|
||||
call void asm sideeffect "mtvrd 2,0", ""()
|
||||
call void asm sideeffect "mtvsrwa 33,0", ""()
|
||||
call void asm sideeffect "mtfprwa 3,0", ""()
|
||||
call void asm sideeffect "mtvrwa 2,0", ""()
|
||||
call void asm sideeffect "mtvsrwz 33,0", ""()
|
||||
call void asm sideeffect "mtfprwz 3,0", ""()
|
||||
call void asm sideeffect "mtvrwz 2,0", ""()
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -45,8 +45,8 @@ define ppc_fp128 @test(%struct.S* byval %x) nounwind {
|
||||
;
|
||||
; CHECK-P9-LABEL: test:
|
||||
; CHECK-P9: # %bb.0: # %entry
|
||||
; CHECK-P9-NEXT: mtvsrd 1, 5
|
||||
; CHECK-P9-NEXT: mtvsrd 2, 6
|
||||
; CHECK-P9-NEXT: mtfprd 1, 5
|
||||
; CHECK-P9-NEXT: mtfprd 2, 6
|
||||
; CHECK-P9-NEXT: std 6, 72(1)
|
||||
; CHECK-P9-NEXT: std 5, 64(1)
|
||||
; CHECK-P9-NEXT: std 3, 48(1)
|
||||
|
||||
@ -11,7 +11,7 @@ define i32 @bad(double %x) {
|
||||
; CHECK: stfd [[REG0]], [[OFF:.*]](1)
|
||||
; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
|
||||
; GENERIC: xscvdpuxws [[REG0:[0-9]+]], 1
|
||||
; GENERIC: mfvsrwz {{[0-9]*}}, [[REG0]]
|
||||
; GENERIC: mffprwz {{[0-9]*}}, [[REG0]]
|
||||
}
|
||||
|
||||
define i32 @bad1(float %x) {
|
||||
@ -23,5 +23,5 @@ entry:
|
||||
; CHECK: stfd [[REG0]], [[OFF:.*]](1)
|
||||
; CHECK: lwa {{[0-9]*}}, [[OFF]](1)
|
||||
; GENERIC: xscvdpsxws [[REG0:[0-9]+]], 1
|
||||
; GENERIC: mfvsrwz {{[0-9]*}}, [[REG0]]
|
||||
; GENERIC: mffprwz {{[0-9]*}}, [[REG0]]
|
||||
}
|
||||
|
||||
@ -10,7 +10,7 @@ entry:
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @foo1
|
||||
; CHECK: mtvsrwz
|
||||
; CHECK: mtfprwz
|
||||
}
|
||||
|
||||
define void @foo2(i16* %p) {
|
||||
@ -21,6 +21,6 @@ entry:
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @foo2
|
||||
; CHECK: mtvsrwz
|
||||
; CHECK: mtfprwz
|
||||
}
|
||||
|
||||
|
||||
@ -23,7 +23,7 @@ define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_add
|
||||
; CHECK-NEXT: lwz 4, 8(3)
|
||||
; CHECK-NEXT: lwz 3, 12(3)
|
||||
; CHECK-NEXT: add 3, 3, 4
|
||||
; CHECK-NEXT: mtvsrwa 0, 3
|
||||
; CHECK-NEXT: mtfprwa 0, 3
|
||||
; CHECK-NEXT: xscvsxdsp 1, 0
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
|
||||
@ -26,7 +26,7 @@ entry:
|
||||
; CHECK-DAG: mffs 1
|
||||
; CHECK-DAG: mffprd [[REG1:[0-9]+]], 1
|
||||
; CHECK-DAG: rldimi [[REG1]], 3, 0, 62
|
||||
; CHECK-DAG: mtvsrd [[REG2:[0-9]+]], [[REG1]]
|
||||
; CHECK-DAG: mtfprd [[REG2:[0-9]+]], [[REG1]]
|
||||
; CHECK-DAG: mtfsf 255, [[REG2]]
|
||||
; CHECK: blr
|
||||
|
||||
|
||||
@ -66,7 +66,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: dpConv2shw
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -88,7 +88,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: dpConv2sb
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -152,7 +152,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: spConv2shw
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -174,7 +174,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: spConv2sb
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -253,7 +253,7 @@ entry:
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -278,7 +278,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: dpConv2sb_x
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -357,7 +357,7 @@ entry:
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -382,7 +382,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: spConv2sb_x
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -450,7 +450,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: dpConv2uhw
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -472,7 +472,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: dpConv2ub
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -536,7 +536,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: spConv2uhw
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -558,7 +558,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: spConv2ub
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -637,7 +637,7 @@ entry:
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -662,7 +662,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: dpConv2ub_x
|
||||
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -741,7 +741,7 @@ entry:
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
@ -766,7 +766,7 @@ entry:
|
||||
; CHECK-PWR8-LABEL: spConv2ub_x
|
||||
; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
|
||||
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
|
||||
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
|
||||
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
|
||||
; CHECK-PWR8-NEXT: blr
|
||||
}
|
||||
|
||||
@ -17,11 +17,11 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
|
||||
; P9BE-NEXT: li r3, 0
|
||||
; P9BE-NEXT: vextuhlx r3, r3, v2
|
||||
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; P9BE-NEXT: mtvsrwz f0, r3
|
||||
; P9BE-NEXT: mtfprwz f0, r3
|
||||
; P9BE-NEXT: li r3, 2
|
||||
; P9BE-NEXT: vextuhlx r3, r3, v2
|
||||
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; P9BE-NEXT: mtvsrwz f1, r3
|
||||
; P9BE-NEXT: mtfprwz f1, r3
|
||||
; P9BE-NEXT: xscvuxddp f0, f0
|
||||
; P9BE-NEXT: xscvuxddp f1, f1
|
||||
; P9BE-NEXT: xxmrghd v2, vs0, vs1
|
||||
@ -32,11 +32,11 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
|
||||
; P9LE-NEXT: li r3, 0
|
||||
; P9LE-NEXT: vextuhrx r3, r3, v2
|
||||
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; P9LE-NEXT: mtvsrwz f0, r3
|
||||
; P9LE-NEXT: mtfprwz f0, r3
|
||||
; P9LE-NEXT: li r3, 2
|
||||
; P9LE-NEXT: vextuhrx r3, r3, v2
|
||||
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; P9LE-NEXT: mtvsrwz f1, r3
|
||||
; P9LE-NEXT: mtfprwz f1, r3
|
||||
; P9LE-NEXT: xscvuxddp f0, f0
|
||||
; P9LE-NEXT: xscvuxddp f1, f1
|
||||
; P9LE-NEXT: xxmrghd v2, vs1, vs0
|
||||
@ -49,8 +49,8 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
|
||||
; P8BE-NEXT: rldicl r3, r3, 32, 48
|
||||
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31
|
||||
; P8BE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; P8BE-NEXT: mtvsrwz f0, r4
|
||||
; P8BE-NEXT: mtvsrwz f1, r3
|
||||
; P8BE-NEXT: mtfprwz f0, r4
|
||||
; P8BE-NEXT: mtfprwz f1, r3
|
||||
; P8BE-NEXT: xscvuxddp f0, f0
|
||||
; P8BE-NEXT: xscvuxddp f1, f1
|
||||
; P8BE-NEXT: xxmrghd v2, vs0, vs1
|
||||
@ -64,8 +64,8 @@ define dso_local <2 x double> @test1(<8 x i16> %a) {
|
||||
; P8LE-NEXT: rldicl r3, r3, 48, 48
|
||||
; P8LE-NEXT: rlwinm r4, r4, 0, 16, 31
|
||||
; P8LE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; P8LE-NEXT: mtvsrwz f0, r4
|
||||
; P8LE-NEXT: mtvsrwz f1, r3
|
||||
; P8LE-NEXT: mtfprwz f0, r4
|
||||
; P8LE-NEXT: mtfprwz f1, r3
|
||||
; P8LE-NEXT: xscvuxddp f0, f0
|
||||
; P8LE-NEXT: xscvuxddp f1, f1
|
||||
; P8LE-NEXT: xxmrghd v2, vs1, vs0
|
||||
@ -103,10 +103,10 @@ define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
|
||||
; P8BE: # %bb.0: # %entry
|
||||
; P8BE-NEXT: xxsldwi vs0, v2, v2, 3
|
||||
; P8BE-NEXT: mfvsrwz r4, v3
|
||||
; P8BE-NEXT: mtvsrwz f1, r4
|
||||
; P8BE-NEXT: mtfprwz f1, r4
|
||||
; P8BE-NEXT: mfvsrwz r3, f0
|
||||
; P8BE-NEXT: xscvuxddp f1, f1
|
||||
; P8BE-NEXT: mtvsrwz f0, r3
|
||||
; P8BE-NEXT: mtfprwz f0, r3
|
||||
; P8BE-NEXT: xscvuxddp f0, f0
|
||||
; P8BE-NEXT: xxmrghd v2, vs0, vs1
|
||||
; P8BE-NEXT: blr
|
||||
@ -117,8 +117,8 @@ define dso_local <2 x double> @test2(<4 x i32> %a, <4 x i32> %b) {
|
||||
; P8LE-NEXT: xxsldwi vs1, v3, v3, 1
|
||||
; P8LE-NEXT: mfvsrwz r3, f0
|
||||
; P8LE-NEXT: mfvsrwz r4, f1
|
||||
; P8LE-NEXT: mtvsrwz f0, r3
|
||||
; P8LE-NEXT: mtvsrwz f1, r4
|
||||
; P8LE-NEXT: mtfprwz f0, r3
|
||||
; P8LE-NEXT: mtfprwz f1, r4
|
||||
; P8LE-NEXT: xscvuxddp f0, f0
|
||||
; P8LE-NEXT: xscvuxddp f1, f1
|
||||
; P8LE-NEXT: xxmrghd v2, vs1, vs0
|
||||
|
||||
@ -9,7 +9,7 @@ entry:
|
||||
%conv = uitofp i16 %0 to ppc_fp128
|
||||
ret ppc_fp128 %conv
|
||||
; CHECK: lhz [[LD:[0-9]+]], 0(3)
|
||||
; CHECK: mtvsrwa [[MV:[0-9]+]], [[LD]]
|
||||
; CHECK: mtfprwa [[MV:[0-9]+]], [[LD]]
|
||||
; CHECK: xscvsxddp [[CONV:[0-9]+]], [[MV]]
|
||||
; CHECK: bl __gcc_qadd
|
||||
}
|
||||
|
||||
@ -29,11 +29,11 @@ define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
|
||||
; CHECK-P9-LABEL: test2elt:
|
||||
; CHECK-P9: # %bb.0: # %entry
|
||||
; CHECK-P9-NEXT: xscvdpuxws f0, v2
|
||||
; CHECK-P9-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-P9-NEXT: mffprwz r3, f0
|
||||
; CHECK-P9-NEXT: xxswapd vs0, v2
|
||||
; CHECK-P9-NEXT: mtvsrws v3, r3
|
||||
; CHECK-P9-NEXT: xscvdpuxws f0, f0
|
||||
; CHECK-P9-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-P9-NEXT: mffprwz r3, f0
|
||||
; CHECK-P9-NEXT: mtvsrws v2, r3
|
||||
; CHECK-P9-NEXT: vmrglw v2, v3, v2
|
||||
; CHECK-P9-NEXT: mfvsrld r3, v2
|
||||
@ -42,11 +42,11 @@ define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
|
||||
; CHECK-BE-LABEL: test2elt:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE-NEXT: xscvdpuxws f0, v2
|
||||
; CHECK-BE-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-BE-NEXT: mffprwz r3, f0
|
||||
; CHECK-BE-NEXT: xxswapd vs0, v2
|
||||
; CHECK-BE-NEXT: mtvsrws v3, r3
|
||||
; CHECK-BE-NEXT: xscvdpuxws f0, f0
|
||||
; CHECK-BE-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-BE-NEXT: mffprwz r3, f0
|
||||
; CHECK-BE-NEXT: mtvsrws v2, r3
|
||||
; CHECK-BE-NEXT: vmrghw v2, v3, v2
|
||||
; CHECK-BE-NEXT: mfvsrd r3, v2
|
||||
@ -323,11 +323,11 @@ define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
|
||||
; CHECK-P9-LABEL: test2elt_signed:
|
||||
; CHECK-P9: # %bb.0: # %entry
|
||||
; CHECK-P9-NEXT: xscvdpsxws f0, v2
|
||||
; CHECK-P9-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-P9-NEXT: mffprwz r3, f0
|
||||
; CHECK-P9-NEXT: xxswapd vs0, v2
|
||||
; CHECK-P9-NEXT: mtvsrws v3, r3
|
||||
; CHECK-P9-NEXT: xscvdpsxws f0, f0
|
||||
; CHECK-P9-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-P9-NEXT: mffprwz r3, f0
|
||||
; CHECK-P9-NEXT: mtvsrws v2, r3
|
||||
; CHECK-P9-NEXT: vmrglw v2, v3, v2
|
||||
; CHECK-P9-NEXT: mfvsrld r3, v2
|
||||
@ -336,11 +336,11 @@ define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
|
||||
; CHECK-BE-LABEL: test2elt_signed:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE-NEXT: xscvdpsxws f0, v2
|
||||
; CHECK-BE-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-BE-NEXT: mffprwz r3, f0
|
||||
; CHECK-BE-NEXT: xxswapd vs0, v2
|
||||
; CHECK-BE-NEXT: mtvsrws v3, r3
|
||||
; CHECK-BE-NEXT: xscvdpsxws f0, f0
|
||||
; CHECK-BE-NEXT: mfvsrwz r3, f0
|
||||
; CHECK-BE-NEXT: mffprwz r3, f0
|
||||
; CHECK-BE-NEXT: mtvsrws v2, r3
|
||||
; CHECK-BE-NEXT: vmrghw v2, v3, v2
|
||||
; CHECK-BE-NEXT: mfvsrd r3, v2
|
||||
|
||||
@ -18,8 +18,8 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
|
||||
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 16, 31
|
||||
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; CHECK-P8-NEXT: mtvsrwz f0, r4
|
||||
; CHECK-P8-NEXT: mtvsrwz f1, r3
|
||||
; CHECK-P8-NEXT: mtfprwz f0, r4
|
||||
; CHECK-P8-NEXT: mtfprwz f1, r3
|
||||
; CHECK-P8-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-P8-NEXT: xscvuxdsp f1, f1
|
||||
; CHECK-P8-NEXT: xscvdpspn vs0, f0
|
||||
@ -37,14 +37,14 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P9-NEXT: li r3, 0
|
||||
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; CHECK-P9-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwz f0, r3
|
||||
; CHECK-P9-NEXT: li r3, 2
|
||||
; CHECK-P9-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
|
||||
; CHECK-P9-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwz f0, r3
|
||||
; CHECK-P9-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
|
||||
@ -58,13 +58,13 @@ define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-BE-NEXT: li r3, 2
|
||||
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
|
||||
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; CHECK-BE-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwz f0, r3
|
||||
; CHECK-BE-NEXT: li r3, 0
|
||||
; CHECK-BE-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
|
||||
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31
|
||||
; CHECK-BE-NEXT: xscvdpspn v3, f0
|
||||
; CHECK-BE-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwz f0, r3
|
||||
; CHECK-BE-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-BE-NEXT: xscvdpspn v2, f0
|
||||
; CHECK-BE-NEXT: vmrghw v2, v2, v3
|
||||
@ -270,8 +270,8 @@ define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
|
||||
; CHECK-P8-NEXT: extsh r4, r4
|
||||
; CHECK-P8-NEXT: extsh r3, r3
|
||||
; CHECK-P8-NEXT: mtvsrwa f0, r4
|
||||
; CHECK-P8-NEXT: mtvsrwa f1, r3
|
||||
; CHECK-P8-NEXT: mtfprwa f0, r4
|
||||
; CHECK-P8-NEXT: mtfprwa f1, r3
|
||||
; CHECK-P8-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-P8-NEXT: xscvsxdsp f1, f1
|
||||
; CHECK-P8-NEXT: xscvdpspn vs0, f0
|
||||
@ -289,14 +289,14 @@ define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P9-NEXT: li r3, 0
|
||||
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: extsh r3, r3
|
||||
; CHECK-P9-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwa f0, r3
|
||||
; CHECK-P9-NEXT: li r3, 2
|
||||
; CHECK-P9-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: vextuhrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: extsh r3, r3
|
||||
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
|
||||
; CHECK-P9-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwa f0, r3
|
||||
; CHECK-P9-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
|
||||
@ -310,13 +310,13 @@ define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-BE-NEXT: li r3, 2
|
||||
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
|
||||
; CHECK-BE-NEXT: extsh r3, r3
|
||||
; CHECK-BE-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwa f0, r3
|
||||
; CHECK-BE-NEXT: li r3, 0
|
||||
; CHECK-BE-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-BE-NEXT: vextuhlx r3, r3, v2
|
||||
; CHECK-BE-NEXT: extsh r3, r3
|
||||
; CHECK-BE-NEXT: xscvdpspn v3, f0
|
||||
; CHECK-BE-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwa f0, r3
|
||||
; CHECK-BE-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-BE-NEXT: xscvdpspn v2, f0
|
||||
; CHECK-BE-NEXT: vmrghw v2, v2, v3
|
||||
|
||||
@ -18,8 +18,8 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
|
||||
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 24, 31
|
||||
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 24, 31
|
||||
; CHECK-P8-NEXT: mtvsrwz f0, r4
|
||||
; CHECK-P8-NEXT: mtvsrwz f1, r3
|
||||
; CHECK-P8-NEXT: mtfprwz f0, r4
|
||||
; CHECK-P8-NEXT: mtfprwz f1, r3
|
||||
; CHECK-P8-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-P8-NEXT: xscvuxdsp f1, f1
|
||||
; CHECK-P8-NEXT: xscvdpspn vs0, f0
|
||||
@ -37,14 +37,14 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P9-NEXT: li r3, 0
|
||||
; CHECK-P9-NEXT: vextubrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
|
||||
; CHECK-P9-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwz f0, r3
|
||||
; CHECK-P9-NEXT: li r3, 1
|
||||
; CHECK-P9-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: vextubrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31
|
||||
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
|
||||
; CHECK-P9-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwz f0, r3
|
||||
; CHECK-P9-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
|
||||
@ -58,13 +58,13 @@ define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-BE-NEXT: li r3, 1
|
||||
; CHECK-BE-NEXT: vextublx r3, r3, v2
|
||||
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
|
||||
; CHECK-BE-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwz f0, r3
|
||||
; CHECK-BE-NEXT: li r3, 0
|
||||
; CHECK-BE-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-BE-NEXT: vextublx r3, r3, v2
|
||||
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31
|
||||
; CHECK-BE-NEXT: xscvdpspn v3, f0
|
||||
; CHECK-BE-NEXT: mtvsrwz f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwz f0, r3
|
||||
; CHECK-BE-NEXT: xscvuxdsp f0, f0
|
||||
; CHECK-BE-NEXT: xscvdpspn v2, f0
|
||||
; CHECK-BE-NEXT: vmrghw v2, v2, v3
|
||||
@ -286,8 +286,8 @@ define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
|
||||
; CHECK-P8-NEXT: extsb r4, r4
|
||||
; CHECK-P8-NEXT: extsb r3, r3
|
||||
; CHECK-P8-NEXT: mtvsrwa f0, r4
|
||||
; CHECK-P8-NEXT: mtvsrwa f1, r3
|
||||
; CHECK-P8-NEXT: mtfprwa f0, r4
|
||||
; CHECK-P8-NEXT: mtfprwa f1, r3
|
||||
; CHECK-P8-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-P8-NEXT: xscvsxdsp f1, f1
|
||||
; CHECK-P8-NEXT: xscvdpspn vs0, f0
|
||||
@ -305,14 +305,14 @@ define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-P9-NEXT: li r3, 0
|
||||
; CHECK-P9-NEXT: vextubrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: extsb r3, r3
|
||||
; CHECK-P9-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwa f0, r3
|
||||
; CHECK-P9-NEXT: li r3, 1
|
||||
; CHECK-P9-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: vextubrx r3, r3, v2
|
||||
; CHECK-P9-NEXT: extsb r3, r3
|
||||
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
|
||||
; CHECK-P9-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-P9-NEXT: mtfprwa f0, r3
|
||||
; CHECK-P9-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-P9-NEXT: xscvdpspn vs0, f0
|
||||
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
|
||||
@ -326,13 +326,13 @@ define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
|
||||
; CHECK-BE-NEXT: li r3, 1
|
||||
; CHECK-BE-NEXT: vextublx r3, r3, v2
|
||||
; CHECK-BE-NEXT: extsb r3, r3
|
||||
; CHECK-BE-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwa f0, r3
|
||||
; CHECK-BE-NEXT: li r3, 0
|
||||
; CHECK-BE-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-BE-NEXT: vextublx r3, r3, v2
|
||||
; CHECK-BE-NEXT: extsb r3, r3
|
||||
; CHECK-BE-NEXT: xscvdpspn v3, f0
|
||||
; CHECK-BE-NEXT: mtvsrwa f0, r3
|
||||
; CHECK-BE-NEXT: mtfprwa f0, r3
|
||||
; CHECK-BE-NEXT: xscvsxdsp f0, f0
|
||||
; CHECK-BE-NEXT: xscvdpspn v2, f0
|
||||
; CHECK-BE-NEXT: vmrghw v2, v2, v3
|
||||
|
||||
@ -528,16 +528,31 @@
|
||||
# CHECK: mfvsrd 3, 40
|
||||
0x7d 0x03 0x00 0x67
|
||||
|
||||
# CHECK: mfvsrwz 5, 0
|
||||
# CHECK: mffprd 3, 0
|
||||
0x7c 0x03 0x00 0x66
|
||||
|
||||
# CHECK: mfvsrwz 5, 40
|
||||
0x7d 0x05 0x00 0xe7
|
||||
|
||||
# CHECK: mffprwz 5, 0
|
||||
0x7c 0x05 0x00 0xe6
|
||||
|
||||
# CHECK: mtvsrd 0, 3
|
||||
# CHECK: mtvsrd 40, 3
|
||||
0x7d 0x03 0x01 0x67
|
||||
|
||||
# CHECK: mtfprd 0, 3
|
||||
0x7c 0x03 0x01 0x66
|
||||
|
||||
# CHECK: mtvsrwa 0, 3
|
||||
# CHECK: mtvsrwa 40, 3
|
||||
0x7d 0x03 0x01 0xa7
|
||||
|
||||
# CHECK: mtfprwa 0, 3
|
||||
0x7c 0x03 0x01 0xa6
|
||||
|
||||
# CHECK: mtvsrwz 0, 3
|
||||
# CHECK: mtvsrwz 40, 3
|
||||
0x7d 0x03 0x01 0xe7
|
||||
|
||||
# CHECK: mtfprwz 0, 3
|
||||
0x7c 0x03 0x01 0xe6
|
||||
|
||||
# Power9 Instructions:
|
||||
|
||||
@ -538,18 +538,64 @@
|
||||
# CHECK-BE: mfvsrd 3, 40 # encoding: [0x7d,0x03,0x00,0x67]
|
||||
# CHECK-LE: mfvsrd 3, 40 # encoding: [0x67,0x00,0x03,0x7d]
|
||||
mfvrd 3, 8
|
||||
# CHECK-BE: mfvsrwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
|
||||
# CHECK-LE: mfvsrwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
|
||||
# CHECK-BE: mffprd 0, 3 # encoding: [0x7c,0x60,0x00,0x66]
|
||||
# CHECK-LE: mffprd 0, 3 # encoding: [0x66,0x00,0x60,0x7c]
|
||||
mfvsrd 0, 3
|
||||
# CHECK-BE: mffprd 0, 3 # encoding: [0x7c,0x60,0x00,0x66]
|
||||
# CHECK-LE: mffprd 0, 3 # encoding: [0x66,0x00,0x60,0x7c]
|
||||
mffprd 0, 3
|
||||
|
||||
# CHECK-BE: mfvsrwz 5, 40 # encoding: [0x7d,0x05,0x00,0xe7]
|
||||
# CHECK-LE: mfvsrwz 5, 40 # encoding: [0xe7,0x00,0x05,0x7d]
|
||||
mfvsrwz 5, 40
|
||||
# CHECK-BE: mfvsrwz 5, 40 # encoding: [0x7d,0x05,0x00,0xe7]
|
||||
# CHECK-LE: mfvsrwz 5, 40 # encoding: [0xe7,0x00,0x05,0x7d]
|
||||
mfvrwz 5, 8
|
||||
# CHECK-BE: mffprwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
|
||||
# CHECK-LE: mffprwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
|
||||
mfvsrwz 5, 0
|
||||
# CHECK-BE: mtvsrd 0, 3 # encoding: [0x7c,0x03,0x01,0x66]
|
||||
# CHECK-LE: mtvsrd 0, 3 # encoding: [0x66,0x01,0x03,0x7c]
|
||||
# CHECK-BE: mffprwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
|
||||
# CHECK-LE: mffprwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
|
||||
mffprwz 5, 0
|
||||
|
||||
# CHECK-BE: mtvsrd 40, 3 # encoding: [0x7d,0x03,0x01,0x67]
|
||||
# CHECK-LE: mtvsrd 40, 3 # encoding: [0x67,0x01,0x03,0x7d]
|
||||
mtvsrd 40, 3
|
||||
# CHECK-BE: mtvsrd 40, 3 # encoding: [0x7d,0x03,0x01,0x67]
|
||||
# CHECK-LE: mtvsrd 40, 3 # encoding: [0x67,0x01,0x03,0x7d]
|
||||
mtvrd 8, 3
|
||||
# CHECK-BE: mtfprd 0, 3 # encoding: [0x7c,0x03,0x01,0x66]
|
||||
# CHECK-LE: mtfprd 0, 3 # encoding: [0x66,0x01,0x03,0x7c]
|
||||
mtvsrd 0, 3
|
||||
# CHECK-BE: mtvsrwa 0, 3 # encoding: [0x7c,0x03,0x01,0xa6]
|
||||
# CHECK-LE: mtvsrwa 0, 3 # encoding: [0xa6,0x01,0x03,0x7c]
|
||||
# CHECK-BE: mtfprd 0, 3 # encoding: [0x7c,0x03,0x01,0x66]
|
||||
# CHECK-LE: mtfprd 0, 3 # encoding: [0x66,0x01,0x03,0x7c]
|
||||
mtfprd 0, 3
|
||||
|
||||
# CHECK-BE: mtvsrwa 40, 3 # encoding: [0x7d,0x03,0x01,0xa7]
|
||||
# CHECK-LE: mtvsrwa 40, 3 # encoding: [0xa7,0x01,0x03,0x7d]
|
||||
mtvsrwa 40, 3
|
||||
# CHECK-BE: mtvsrwa 40, 3 # encoding: [0x7d,0x03,0x01,0xa7]
|
||||
# CHECK-LE: mtvsrwa 40, 3 # encoding: [0xa7,0x01,0x03,0x7d]
|
||||
mtvrwa 8, 3
|
||||
# CHECK-BE: mtfprwa 0, 3 # encoding: [0x7c,0x03,0x01,0xa6]
|
||||
# CHECK-LE: mtfprwa 0, 3 # encoding: [0xa6,0x01,0x03,0x7c]
|
||||
mtvsrwa 0, 3
|
||||
# CHECK-BE: mtvsrwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6]
|
||||
# CHECK-LE: mtvsrwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c]
|
||||
# CHECK-BE: mtfprwa 0, 3 # encoding: [0x7c,0x03,0x01,0xa6]
|
||||
# CHECK-LE: mtfprwa 0, 3 # encoding: [0xa6,0x01,0x03,0x7c]
|
||||
mtfprwa 0, 3
|
||||
|
||||
# CHECK-BE: mtvsrwz 40, 3 # encoding: [0x7d,0x03,0x01,0xe7]
|
||||
# CHECK-LE: mtvsrwz 40, 3 # encoding: [0xe7,0x01,0x03,0x7d]
|
||||
mtvsrwz 40, 3
|
||||
# CHECK-BE: mtvsrwz 40, 3 # encoding: [0x7d,0x03,0x01,0xe7]
|
||||
# CHECK-LE: mtvsrwz 40, 3 # encoding: [0xe7,0x01,0x03,0x7d]
|
||||
mtvrwz 8, 3
|
||||
# CHECK-BE: mtfprwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6]
|
||||
# CHECK-LE: mtfprwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c]
|
||||
mtvsrwz 0, 3
|
||||
# CHECK-BE: mtfprwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6]
|
||||
# CHECK-LE: mtfprwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c]
|
||||
mtfprwz 0, 3
|
||||
|
||||
# Power9 Instructions:
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user