mirror of
https://github.com/RPCS3/llvm-mirror.git
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Reapply r206732. This time without optimization of branches.
llvm-svn: 206749
This commit is contained in:
Michael Zolotukhin
parent
d8c4c53242
commit
c7f992f9a3
@ -444,6 +444,19 @@ def int_umul_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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def int_safe_udiv : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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def int_safe_urem : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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def int_safe_sdiv : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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def int_safe_srem : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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//===------------------------- Memory Use Markers -------------------------===//
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//
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def int_lifetime_start : Intrinsic<[],
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@ -218,6 +218,10 @@ public:
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/// Return true if pow2 div is cheaper than a chain of srl/add/sra.
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bool isPow2DivCheap() const { return Pow2DivIsCheap; }
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/// Return true if Div never traps, returns 0 when div by 0 and return TMin,
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/// when sdiv TMin by -1.
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bool isDivWellDefined() const { return DivIsWellDefined; }
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/// Return true if Flow Control is an expensive operation that should be
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/// avoided.
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bool isJumpExpensive() const { return JumpIsExpensive; }
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@ -1026,6 +1030,13 @@ protected:
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/// signed divide by power of two, and let the target handle it.
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void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
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/// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem
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/// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is
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/// SignedMinValue and RHS is -1.
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void setDivIsWellDefined (bool isWellDefined = true) {
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DivIsWellDefined = isWellDefined;
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}
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/// Add the specified register class as an available regclass for the
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/// specified value type. This indicates the selector can handle values of
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/// that class natively.
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@ -1441,6 +1452,11 @@ private:
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/// signed divide by power of two, and let the target handle it.
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bool Pow2DivIsCheap;
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/// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem
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/// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is
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/// SignedMinValue and RHS is -1.
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bool DivIsWellDefined;
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/// Tells the code generator that it shouldn't generate extra flow control
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/// instructions and should attempt to combine flow control instructions via
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/// predication.
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@ -688,6 +688,242 @@ bool CodeGenPrepare::OptimizeCallInst(CallInst *CI) {
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}
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return true;
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}
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// Lower all uses of llvm.safe.[us]{div|rem}...
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if (II &&
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(II->getIntrinsicID() == Intrinsic::safe_sdiv ||
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II->getIntrinsicID() == Intrinsic::safe_udiv ||
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II->getIntrinsicID() == Intrinsic::safe_srem ||
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II->getIntrinsicID() == Intrinsic::safe_urem)) {
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// Given
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// result_struct = type {iN, i1}
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// %R = call result_struct llvm.safe.sdiv.iN(iN %x, iN %y)
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// Expand it to actual IR, which produces result to the same variable %R.
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// First element of the result %R.1 is the result of division, second
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// element shows whether the division was correct or not.
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// If %y is 0, %R.1 is 0, %R.2 is 1. (1)
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// If %x is minSignedValue and %y is -1, %R.1 is %x, %R.2 is 1. (2)
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// In other cases %R.1 is (sdiv %x, %y), %R.2 is 0. (3)
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//
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// Similar applies to srem, udiv, and urem builtins, except that in unsigned
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// variants we don't check condition (2).
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bool IsSigned;
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BinaryOperator::BinaryOps Op;
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switch (II->getIntrinsicID()) {
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case Intrinsic::safe_sdiv:
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IsSigned = true;
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Op = Instruction::SDiv;
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break;
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case Intrinsic::safe_udiv:
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IsSigned = false;
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Op = Instruction::UDiv;
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break;
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case Intrinsic::safe_srem:
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IsSigned = true;
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Op = Instruction::SRem;
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break;
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case Intrinsic::safe_urem:
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IsSigned = false;
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Op = Instruction::URem;
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break;
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default:
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llvm_unreachable("Only Div/Rem intrinsics are handled here.");
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}
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Value *LHS = II->getOperand(0), *RHS = II->getOperand(1);
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bool DivWellDefined = TLI && TLI->isDivWellDefined();
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bool ResultNeeded[2] = {false, false};
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SmallVector<User*, 1> ResultsUsers[2];
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bool BadCase = false;
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for (User *U: II->users()) {
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ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
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if (!EVI || EVI->getNumIndices() > 1 || EVI->getIndices()[0] > 1) {
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BadCase = true;
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break;
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}
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ResultNeeded[EVI->getIndices()[0]] = true;
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ResultsUsers[EVI->getIndices()[0]].push_back(U);
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}
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// Behave conservatively, if there is an unusual user of the results.
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if (BadCase)
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ResultNeeded[0] = ResultNeeded[1] = true;
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// Early exit if non of the results is ever used.
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if (!ResultNeeded[0] && !ResultNeeded[1]) {
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II->eraseFromParent();
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return true;
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}
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// Early exit if the second result (flag) isn't used and target
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// div-instruction computes exactly what we want to get as the first result
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// and never traps.
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if (ResultNeeded[0] && !ResultNeeded[1] && DivWellDefined) {
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BinaryOperator *Div = BinaryOperator::Create(Op, LHS, RHS);
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Div->insertAfter(II);
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for (User *U: ResultsUsers[0]) {
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Instruction *UserInst = dyn_cast<Instruction>(U);
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assert(UserInst && "Unexpected null-instruction");
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UserInst->replaceAllUsesWith(Div);
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UserInst->eraseFromParent();
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}
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II->eraseFromParent();
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CurInstIterator = Div;
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ModifiedDT = true;
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return true;
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}
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Value *MinusOne = Constant::getAllOnesValue(LHS->getType());
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Value *Zero = Constant::getNullValue(LHS->getType());
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// Split the original BB and create other basic blocks that will be used
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// for checks.
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BasicBlock *StartBB = II->getParent();
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BasicBlock::iterator SplitPt = ++(BasicBlock::iterator(II));
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BasicBlock *NextBB = StartBB->splitBasicBlock(SplitPt, "div.end");
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BasicBlock *DivByZeroBB;
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DivByZeroBB = BasicBlock::Create(II->getContext(), "div.divz",
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NextBB->getParent(), NextBB);
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BranchInst::Create(NextBB, DivByZeroBB);
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BasicBlock *DivBB = BasicBlock::Create(II->getContext(), "div.div",
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NextBB->getParent(), NextBB);
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BranchInst::Create(NextBB, DivBB);
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// For signed variants, check the condition (2):
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// LHS == SignedMinValue, RHS == -1.
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Value *CmpMinusOne;
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Value *CmpMinValue;
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BasicBlock *ChkDivMinBB;
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BasicBlock *DivMinBB;
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Value *MinValue;
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if (IsSigned) {
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APInt SignedMinValue =
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APInt::getSignedMinValue(LHS->getType()->getPrimitiveSizeInBits());
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MinValue = Constant::getIntegerValue(LHS->getType(), SignedMinValue);
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ChkDivMinBB = BasicBlock::Create(II->getContext(), "div.chkdivmin",
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NextBB->getParent(), NextBB);
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BranchInst::Create(NextBB, ChkDivMinBB);
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DivMinBB = BasicBlock::Create(II->getContext(), "div.divmin",
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NextBB->getParent(), NextBB);
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BranchInst::Create(NextBB, DivMinBB);
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CmpMinusOne = CmpInst::Create(Instruction::ICmp, CmpInst::ICMP_EQ,
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RHS, MinusOne, "cmp.rhs.minus.one",
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ChkDivMinBB->getTerminator());
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CmpMinValue = CmpInst::Create(Instruction::ICmp, CmpInst::ICMP_EQ,
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LHS, MinValue, "cmp.lhs.signed.min",
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ChkDivMinBB->getTerminator());
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BinaryOperator *CmpSignedOvf = BinaryOperator::Create(Instruction::And,
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CmpMinusOne,
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CmpMinValue);
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// Here we're interested in the case when both %x is TMin and %y is -1.
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// In this case the result will overflow.
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// If that's not the case, we can perform usual division. These blocks
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// will be inserted after DivByZero, so the division will be safe.
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CmpSignedOvf->insertBefore(ChkDivMinBB->getTerminator());
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BranchInst::Create(DivMinBB, DivBB, CmpSignedOvf,
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ChkDivMinBB->getTerminator());
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ChkDivMinBB->getTerminator()->eraseFromParent();
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}
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// Check the condition (1):
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// RHS == 0.
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Value *CmpDivZero = CmpInst::Create(Instruction::ICmp, CmpInst::ICMP_EQ,
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RHS, Zero, "cmp.rhs.zero",
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StartBB->getTerminator());
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// If RHS != 0, we want to check condition (2) in signed case, or proceed
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// to usual division in unsigned case.
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BranchInst::Create(DivByZeroBB, IsSigned ? ChkDivMinBB : DivBB, CmpDivZero,
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StartBB->getTerminator());
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StartBB->getTerminator()->eraseFromParent();
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// At the moment we have all the control flow created. We just need to
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// insert DIV and PHI (if needed) to get the result value.
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Instruction *DivRes, *FlagRes;
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Instruction *InsPoint = nullptr;
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if (ResultNeeded[0]) {
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BinaryOperator *Div = BinaryOperator::Create(Op, LHS, RHS);
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if (DivWellDefined) {
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// The result value is the result of DIV operation placed right at the
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// original place of the intrinsic.
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Div->insertAfter(II);
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DivRes = Div;
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} else {
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// The result is a PHI-node.
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Div->insertBefore(DivBB->getTerminator());
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PHINode *DivResPN =
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PHINode::Create(LHS->getType(), IsSigned ? 3 : 2, "div.res.phi",
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NextBB->begin());
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DivResPN->addIncoming(Div, DivBB);
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DivResPN->addIncoming(Zero, DivByZeroBB);
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if (IsSigned)
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DivResPN->addIncoming(MinValue, DivMinBB);
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DivRes = DivResPN;
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InsPoint = DivResPN;
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}
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}
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// Prepare a value for the second result (flag) if it is needed.
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if (ResultNeeded[1]) {
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Type *FlagTy = II->getType()->getStructElementType(1);
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PHINode *FlagResPN =
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PHINode::Create(FlagTy, IsSigned ? 3 : 2, "div.flag.phi",
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NextBB->begin());
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FlagResPN->addIncoming(Constant::getNullValue(FlagTy), DivBB);
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FlagResPN->addIncoming(Constant::getAllOnesValue(FlagTy), DivByZeroBB);
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if (IsSigned)
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FlagResPN->addIncoming(Constant::getAllOnesValue(FlagTy), DivMinBB);
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FlagRes = FlagResPN;
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if (!InsPoint)
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InsPoint = FlagRes;
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}
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// If possible, propagate the results to the user. Otherwise, create alloca,
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// and create a struct with the results on stack.
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if (!BadCase) {
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if (ResultNeeded[0]) {
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for (User *U: ResultsUsers[0]) {
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Instruction *UserInst = dyn_cast<Instruction>(U);
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assert(UserInst && "Unexpected null-instruction");
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UserInst->replaceAllUsesWith(DivRes);
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UserInst->eraseFromParent();
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}
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}
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if (ResultNeeded[1]) {
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for (User *FlagU: ResultsUsers[1]) {
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Instruction *FlagUInst = dyn_cast<Instruction>(FlagU);
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FlagUInst->replaceAllUsesWith(FlagRes);
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FlagUInst->eraseFromParent();
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}
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}
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} else {
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// Create alloca, store our new values to it, and then load the final
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// result from it.
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Constant *Idx0 = ConstantInt::get(Type::getInt32Ty(II->getContext()), 0);
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Constant *Idx1 = ConstantInt::get(Type::getInt32Ty(II->getContext()), 1);
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Value *Idxs_DivRes[2] = {Idx0, Idx0};
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Value *Idxs_FlagRes[2] = {Idx0, Idx1};
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Value *NewRes = new llvm::AllocaInst(II->getType(), 0, "div.res.ptr", II);
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Instruction *ResDivAddr = GetElementPtrInst::Create(NewRes, Idxs_DivRes);
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Instruction *ResFlagAddr =
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GetElementPtrInst::Create(NewRes, Idxs_FlagRes);
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ResDivAddr->insertAfter(InsPoint);
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ResFlagAddr->insertAfter(ResDivAddr);
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StoreInst *StoreResDiv = new StoreInst(DivRes, ResDivAddr);
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StoreInst *StoreResFlag = new StoreInst(FlagRes, ResFlagAddr);
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StoreResDiv->insertAfter(ResFlagAddr);
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StoreResFlag->insertAfter(StoreResDiv);
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LoadInst *LoadRes = new LoadInst(NewRes, "div.res");
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LoadRes->insertAfter(StoreResFlag);
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II->replaceAllUsesWith(LoadRes);
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}
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II->eraseFromParent();
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CurInstIterator = StartBB->end();
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ModifiedDT = true;
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return true;
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}
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if (II && TLI) {
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SmallVector<Value*, 2> PtrOps;
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@ -682,6 +682,7 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
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HasMultipleConditionRegisters = false;
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IntDivIsCheap = false;
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Pow2DivIsCheap = false;
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DivIsWellDefined = false;
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JumpIsExpensive = false;
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PredictableSelectIsExpensive = false;
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MaskAndBranchFoldingIsLegal = false;
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@ -435,6 +435,8 @@ ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM)
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setMinFunctionAlignment(2);
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setDivIsWellDefined(true);
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RequireStrictAlign = StrictAlign;
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}
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83
test/CodeGen/ARM64/SafeDivRemIntrinsics-Opts.ll
Normal file
83
test/CodeGen/ARM64/SafeDivRemIntrinsics-Opts.ll
Normal file
@ -0,0 +1,83 @@
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; RUN: llc < %s -march=arm64 | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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%divovf32 = type { i32, i1 }
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declare %divovf32 @llvm.safe.sdiv.i32(i32, i32) nounwind readnone
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declare %divovf32 @llvm.safe.udiv.i32(i32, i32) nounwind readnone
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; CHECK-LABEL: sdiv32_results_unused
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; CHECK: entry
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; CHECK-NEXT: ret
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define void @sdiv32_results_unused(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
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ret void
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}
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; CHECK-LABEL: sdiv32_div_result_unused
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; CHECK-NOT: sdiv{{[ ]}}
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define i1 @sdiv32_div_result_unused(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
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%bit = extractvalue %divovf32 %divr, 1
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ret i1 %bit
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}
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; CHECK-LABEL: sdiv32_flag_result_unused
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; CHECK-NOT: cb
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; CHECK: sdiv{{[ ]}}
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define i32 @sdiv32_flag_result_unused(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
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%div = extractvalue %divovf32 %divr, 0
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ret i32 %div
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}
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; CHECK-LABEL: sdiv32_result_returned
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; CHECK: sdiv{{[ ]}}
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define %divovf32 @sdiv32_result_returned(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
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ret %divovf32 %divr
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}
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; CHECK-LABEL: udiv32_results_unused
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; CHECK: entry
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; CHECK-NEXT: ret
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define void @udiv32_results_unused(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
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ret void
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}
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; CHECK-LABEL: udiv32_div_result_unused
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; CHECK-NOT: udiv{{[ ]}}
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define i1 @udiv32_div_result_unused(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
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%bit = extractvalue %divovf32 %divr, 1
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ret i1 %bit
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}
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; CHECK-LABEL: udiv32_flag_result_unused
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; CHECK-NOT: cb
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; CHECK: udiv{{[ ]}}
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define i32 @udiv32_flag_result_unused(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
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%div = extractvalue %divovf32 %divr, 0
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ret i32 %div
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}
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; CHECK-LABEL: udiv32_result_returned
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; CHECK: udiv{{[ ]}}
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define %divovf32 @udiv32_result_returned(i32 %x, i32 %y) {
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entry:
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%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
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ret %divovf32 %divr
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}
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!llvm.ident = !{!0}
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!0 = metadata !{metadata !"clang version 3.5.0 "}
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||||
152
test/CodeGen/ARM64/SafeDivRemIntrinsics.ll
Normal file
152
test/CodeGen/ARM64/SafeDivRemIntrinsics.ll
Normal file
@ -0,0 +1,152 @@
|
||||
; RUN: llc < %s -march=arm64 | FileCheck %s
|
||||
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
|
||||
|
||||
%divovf8 = type { i8, i1 }
|
||||
%divovf16 = type { i16, i1 }
|
||||
%divovf32 = type { i32, i1 }
|
||||
%divovf64 = type { i64, i1 }
|
||||
|
||||
declare %divovf8 @llvm.safe.sdiv.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.sdiv.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.sdiv.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.sdiv.i64(i64, i64) nounwind readnone
|
||||
|
||||
declare %divovf8 @llvm.safe.srem.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.srem.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.srem.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.srem.i64(i64, i64) nounwind readnone
|
||||
|
||||
declare %divovf8 @llvm.safe.udiv.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.udiv.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.udiv.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.udiv.i64(i64, i64) nounwind readnone
|
||||
|
||||
declare %divovf8 @llvm.safe.urem.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.urem.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.urem.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.urem.i64(i64, i64) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: sdiv8
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
define %divovf8 @sdiv8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%divr = call %divovf8 @llvm.safe.sdiv.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %divr
|
||||
}
|
||||
; CHECK-LABEL: sdiv16
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
define %divovf16 @sdiv16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%divr = call %divovf16 @llvm.safe.sdiv.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %divr
|
||||
}
|
||||
; CHECK-LABEL: sdiv32
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
define %divovf32 @sdiv32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %divr
|
||||
}
|
||||
; CHECK-LABEL: sdiv64
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
define %divovf64 @sdiv64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%divr = call %divovf64 @llvm.safe.sdiv.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv8
|
||||
; CHECK: udiv{{[ ]}}
|
||||
define %divovf8 @udiv8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%divr = call %divovf8 @llvm.safe.udiv.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv16
|
||||
; CHECK: udiv{{[ ]}}
|
||||
define %divovf16 @udiv16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%divr = call %divovf16 @llvm.safe.udiv.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv32
|
||||
; CHECK: udiv{{[ ]}}
|
||||
define %divovf32 @udiv32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv64
|
||||
; CHECK: udiv{{[ ]}}
|
||||
define %divovf64 @udiv64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%divr = call %divovf64 @llvm.safe.udiv.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %divr
|
||||
}
|
||||
; CHECK-LABEL: srem8
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf8 @srem8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%remr = call %divovf8 @llvm.safe.srem.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %remr
|
||||
}
|
||||
; CHECK-LABEL: srem16
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf16 @srem16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%remr = call %divovf16 @llvm.safe.srem.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %remr
|
||||
}
|
||||
; CHECK-LABEL: srem32
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf32 @srem32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%remr = call %divovf32 @llvm.safe.srem.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %remr
|
||||
}
|
||||
; CHECK-LABEL: srem64
|
||||
; CHECK: sdiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf64 @srem64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%remr = call %divovf64 @llvm.safe.srem.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem8
|
||||
; CHECK: udiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf8 @urem8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%remr = call %divovf8 @llvm.safe.urem.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem16
|
||||
; CHECK: udiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf16 @urem16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%remr = call %divovf16 @llvm.safe.urem.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem32
|
||||
; CHECK: udiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf32 @urem32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%remr = call %divovf32 @llvm.safe.urem.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem64
|
||||
; CHECK: udiv{{[ ]}}
|
||||
; CHECK: msub{{[ ]}}
|
||||
define %divovf64 @urem64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%remr = call %divovf64 @llvm.safe.urem.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %remr
|
||||
}
|
||||
|
||||
!llvm.ident = !{!0}
|
||||
|
||||
!0 = metadata !{metadata !"clang version 3.5.0 "}
|
||||
82
test/CodeGen/X86/SafeDivRemIntrinsics-Opts.ll
Normal file
82
test/CodeGen/X86/SafeDivRemIntrinsics-Opts.ll
Normal file
@ -0,0 +1,82 @@
|
||||
; RUN: llc < %s -march=x86-64 | FileCheck %s
|
||||
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
|
||||
|
||||
%divovf32 = type { i32, i1 }
|
||||
|
||||
declare %divovf32 @llvm.safe.sdiv.i32(i32, i32) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.udiv.i32(i32, i32) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: sdiv32_results_unused
|
||||
; CHECK: entry
|
||||
; CHECK-NEXT: ret
|
||||
define void @sdiv32_results_unused(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sdiv32_div_result_unused
|
||||
; CHECK-NOT: idiv
|
||||
define i1 @sdiv32_div_result_unused(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
|
||||
%bit = extractvalue %divovf32 %divr, 1
|
||||
ret i1 %bit
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sdiv32_flag_result_unused
|
||||
; CHECK: idiv
|
||||
define i32 @sdiv32_flag_result_unused(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
|
||||
%div = extractvalue %divovf32 %divr, 0
|
||||
ret i32 %div
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sdiv32_result_returned
|
||||
; CHECK: idiv
|
||||
define %divovf32 @sdiv32_result_returned(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %divr
|
||||
}
|
||||
|
||||
; CHECK-LABEL: udiv32_results_unused
|
||||
; CHECK: entry
|
||||
; CHECK-NEXT: ret
|
||||
define void @udiv32_results_unused(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: udiv32_div_result_unused
|
||||
; CHECK-NOT: udiv{{[ ]}}
|
||||
define i1 @udiv32_div_result_unused(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
|
||||
%bit = extractvalue %divovf32 %divr, 1
|
||||
ret i1 %bit
|
||||
}
|
||||
|
||||
; CHECK-LABEL: udiv32_flag_result_unused
|
||||
; CHECK-NOT: cb
|
||||
; CHECK: {{[ ]}}div
|
||||
define i32 @udiv32_flag_result_unused(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
|
||||
%div = extractvalue %divovf32 %divr, 0
|
||||
ret i32 %div
|
||||
}
|
||||
|
||||
; CHECK-LABEL: udiv32_result_returned
|
||||
; CHECK: {{[ ]}}div
|
||||
define %divovf32 @udiv32_result_returned(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %divr
|
||||
}
|
||||
|
||||
!llvm.ident = !{!0}
|
||||
|
||||
!0 = metadata !{metadata !"clang version 3.5.0 "}
|
||||
144
test/CodeGen/X86/SafeDivRemIntrinsics.ll
Normal file
144
test/CodeGen/X86/SafeDivRemIntrinsics.ll
Normal file
@ -0,0 +1,144 @@
|
||||
; RUN: llc < %s -march=x86-64 | FileCheck %s
|
||||
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
|
||||
|
||||
%divovf8 = type { i8, i1 }
|
||||
%divovf16 = type { i16, i1 }
|
||||
%divovf32 = type { i32, i1 }
|
||||
%divovf64 = type { i64, i1 }
|
||||
|
||||
declare %divovf8 @llvm.safe.sdiv.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.sdiv.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.sdiv.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.sdiv.i64(i64, i64) nounwind readnone
|
||||
|
||||
declare %divovf8 @llvm.safe.srem.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.srem.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.srem.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.srem.i64(i64, i64) nounwind readnone
|
||||
|
||||
declare %divovf8 @llvm.safe.udiv.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.udiv.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.udiv.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.udiv.i64(i64, i64) nounwind readnone
|
||||
|
||||
declare %divovf8 @llvm.safe.urem.i8(i8, i8) nounwind readnone
|
||||
declare %divovf16 @llvm.safe.urem.i16(i16, i16) nounwind readnone
|
||||
declare %divovf32 @llvm.safe.urem.i32(i32, i32) nounwind readnone
|
||||
declare %divovf64 @llvm.safe.urem.i64(i64, i64) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: sdiv8
|
||||
; CHECK: idivb{{[ ]}}
|
||||
define %divovf8 @sdiv8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%divr = call %divovf8 @llvm.safe.sdiv.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %divr
|
||||
}
|
||||
; CHECK-LABEL: sdiv16
|
||||
; CHECK: idivw{{[ ]}}
|
||||
define %divovf16 @sdiv16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%divr = call %divovf16 @llvm.safe.sdiv.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %divr
|
||||
}
|
||||
; CHECK-LABEL: sdiv32
|
||||
; CHECK: idivl{{[ ]}}
|
||||
define %divovf32 @sdiv32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.sdiv.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %divr
|
||||
}
|
||||
; CHECK-LABEL: sdiv64
|
||||
; CHECK: idivq{{[ ]}}
|
||||
define %divovf64 @sdiv64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%divr = call %divovf64 @llvm.safe.sdiv.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv8
|
||||
; CHECK: {{[ ]}}divb{{[ ]}}
|
||||
define %divovf8 @udiv8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%divr = call %divovf8 @llvm.safe.udiv.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv16
|
||||
; CHECK: {{[ ]}}divw{{[ ]}}
|
||||
define %divovf16 @udiv16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%divr = call %divovf16 @llvm.safe.udiv.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv32
|
||||
; CHECK: {{[ ]}}divl{{[ ]}}
|
||||
define %divovf32 @udiv32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%divr = call %divovf32 @llvm.safe.udiv.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %divr
|
||||
}
|
||||
; CHECK-LABEL: udiv64
|
||||
; CHECK: {{[ ]}}divq{{[ ]}}
|
||||
define %divovf64 @udiv64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%divr = call %divovf64 @llvm.safe.udiv.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %divr
|
||||
}
|
||||
; CHECK-LABEL: srem8
|
||||
; CHECK: idivb{{[ ]}}
|
||||
define %divovf8 @srem8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%remr = call %divovf8 @llvm.safe.srem.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %remr
|
||||
}
|
||||
; CHECK-LABEL: srem16
|
||||
; CHECK: idivw{{[ ]}}
|
||||
define %divovf16 @srem16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%remr = call %divovf16 @llvm.safe.srem.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %remr
|
||||
}
|
||||
; CHECK-LABEL: srem32
|
||||
; CHECK: idivl{{[ ]}}
|
||||
define %divovf32 @srem32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%remr = call %divovf32 @llvm.safe.srem.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %remr
|
||||
}
|
||||
; CHECK-LABEL: srem64
|
||||
; CHECK: idivq{{[ ]}}
|
||||
define %divovf64 @srem64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%remr = call %divovf64 @llvm.safe.srem.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem8
|
||||
; CHECK: {{[ ]}}divb{{[ ]}}
|
||||
define %divovf8 @urem8(i8 %x, i8 %y) {
|
||||
entry:
|
||||
%remr = call %divovf8 @llvm.safe.urem.i8(i8 %x, i8 %y)
|
||||
ret %divovf8 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem16
|
||||
; CHECK: {{[ ]}}divw{{[ ]}}
|
||||
define %divovf16 @urem16(i16 %x, i16 %y) {
|
||||
entry:
|
||||
%remr = call %divovf16 @llvm.safe.urem.i16(i16 %x, i16 %y)
|
||||
ret %divovf16 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem32
|
||||
; CHECK: {{[ ]}}divl{{[ ]}}
|
||||
define %divovf32 @urem32(i32 %x, i32 %y) {
|
||||
entry:
|
||||
%remr = call %divovf32 @llvm.safe.urem.i32(i32 %x, i32 %y)
|
||||
ret %divovf32 %remr
|
||||
}
|
||||
; CHECK-LABEL: urem64
|
||||
; CHECK: {{[ ]}}divq{{[ ]}}
|
||||
define %divovf64 @urem64(i64 %x, i64 %y) {
|
||||
entry:
|
||||
%remr = call %divovf64 @llvm.safe.urem.i64(i64 %x, i64 %y)
|
||||
ret %divovf64 %remr
|
||||
}
|
||||
|
||||
!llvm.ident = !{!0}
|
||||
|
||||
!0 = metadata !{metadata !"clang version 3.5.0 "}
|
||||
Loading…
Reference in New Issue
Block a user