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[mips] Implement the 'dext' aliases and it's disassembly alias.
The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276
This commit is contained in:
Simon Dardis
parent
18cd6e29b7
commit
c8036cbb4c
@ -465,6 +465,7 @@ public:
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Match_NonZeroOperandForSync,
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Match_RequiresPosSizeRange0_32,
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Match_RequiresPosSizeRange33_64,
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Match_RequiresPosSizeUImm6,
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#define GET_OPERAND_DIAGNOSTIC_TYPES
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#include "MipsGenAsmMatcher.inc"
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#undef GET_OPERAND_DIAGNOSTIC_TYPES
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@ -4979,28 +4980,50 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
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return Match_RequiresDifferentOperands;
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return Match_Success;
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case Mips::DINS:
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case Mips::DINS_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for dins!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((0 > (Pos + Size)) || ((Pos + Size) > 32))
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return Match_RequiresPosSizeRange0_32;
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return Match_Success;
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}
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case Mips::DINSM:
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case Mips::DINSM_MM64R6:
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case Mips::DINSU:
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case Mips::DINSU_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for dinsm/dinsu!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((32 >= (Pos + Size)) || ((Pos + Size) > 64))
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return Match_RequiresPosSizeRange33_64;
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return Match_Success;
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}
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case Mips::DINS:
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case Mips::DINS_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for dins!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((0 > (Pos + Size)) || ((Pos + Size) > 32))
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return Match_RequiresPosSizeRange0_32;
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return Match_Success;
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}
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case Mips::DINSM:
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case Mips::DINSM_MM64R6:
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case Mips::DINSU:
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case Mips::DINSU_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for dinsm/dinsu!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((32 >= (Pos + Size)) || ((Pos + Size) > 64))
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return Match_RequiresPosSizeRange33_64;
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return Match_Success;
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}
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case Mips::DEXT:
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case Mips::DEXT_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for DEXTM!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((1 > (Pos + Size)) || ((Pos + Size) > 63))
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return Match_RequiresPosSizeUImm6;
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return Match_Success;
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}
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case Mips::DEXTM:
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case Mips::DEXTU:
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case Mips::DEXTM_MM64R6:
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case Mips::DEXTU_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for dextm/dextu!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((32 > (Pos + Size)) || ((Pos + Size) > 64))
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return Match_RequiresPosSizeRange33_64;
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return Match_Success;
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}
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}
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uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags;
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@ -5199,6 +5222,12 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return Error(ErrorStart, "size plus position are not in the range 0 .. 32",
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SMRange(ErrorStart, ErrorEnd));
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}
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case Match_RequiresPosSizeUImm6: {
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SMLoc ErrorStart = Operands[3]->getStartLoc();
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SMLoc ErrorEnd = Operands[4]->getEndLoc();
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return Error(ErrorStart, "size plus position are not in the range 1 .. 63",
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SMRange(ErrorStart, ErrorEnd));
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}
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case Match_RequiresPosSizeRange33_64: {
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SMLoc ErrorStart = Operands[3]->getStartLoc();
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SMLoc ErrorEnd = Operands[4]->getEndLoc();
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@ -523,6 +523,10 @@ template <typename InsnType>
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static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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@ -1055,6 +1059,60 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
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return MCDisassembler::Success;
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}
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// Override the generated disassembler to produce DEXT all the time. This is
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// for feature / behaviour parity with binutils.
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template <typename InsnType>
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static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
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unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
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unsigned Size = 0;
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unsigned Pos = 0;
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bool IsMicroMips = false;
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switch (MI.getOpcode()) {
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case Mips::DEXT_MM64R6:
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IsMicroMips = true;
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LLVM_FALLTHROUGH;
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case Mips::DEXT:
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Pos = Lsb;
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Size = Msbd + 1;
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break;
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case Mips::DEXTM_MM64R6:
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IsMicroMips = true;
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LLVM_FALLTHROUGH;
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case Mips::DEXTM:
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Pos = Lsb;
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Size = Msbd + 1 + 32;
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break;
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case Mips::DEXTU_MM64R6:
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IsMicroMips = true;
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LLVM_FALLTHROUGH;
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case Mips::DEXTU:
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Pos = Lsb + 32;
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Size = Msbd + 1;
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break;
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default:
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llvm_unreachable("Unknown DEXT instruction!");
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}
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MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT);
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// Although the format of the instruction is similar, rs and rt are swapped
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// for microMIPS64R6.
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InsnType Rs = fieldFromInstruction(Insn, 21, 5);
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InsnType Rt = fieldFromInstruction(Insn, 16, 5);
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if (IsMicroMips)
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std::swap(Rs, Rt);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
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MI.addOperand(MCOperand::createImm(Pos));
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MI.addOperand(MCOperand::createImm(Size));
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return MCDisassembler::Success;
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}
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// Override the generated disassembler to produce DINS all the time. This is
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// for feature / behaviour parity with binutils.
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template <typename InsnType>
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@ -111,11 +111,8 @@ class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
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Format Form = FrmR;
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string BaseOpcode = instr_asm;
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}
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// TODO: Add 'pos + size' constraint check to dext* instructions
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// DEXT: 0 < pos + size <= 63
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// DEXTM, DEXTU: 32 < pos + size <= 64
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class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
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uimm5_plus1, MipsExt>;
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uimm5_plus1_report_uimm6, MipsExt>;
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class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
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uimm5_plus33, MipsExt>;
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class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
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@ -367,12 +364,14 @@ let DecoderNamespace = "MicroMipsR6" in {
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def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
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def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
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}
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def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
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ISA_MICROMIPS64R6;
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let DecoderMethod = "DecodeDEXT" in {
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def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
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ISA_MICROMIPS64R6;
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}
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def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
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ISA_MICROMIPS64R6;
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def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
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@ -572,3 +571,12 @@ def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
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(DINSU_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs,
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uimm5_plus32:$pos, uimm5_plus1:$size), 0>,
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ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
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(DEXTM_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
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uimm5_plus33:$size), 0>,
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ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
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(DEXTU_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs,
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uimm5_plus32:$pos, uimm5_plus1:$size), 0>,
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ISA_MICROMIPS64R6;
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@ -317,16 +317,22 @@ let isCodeGenOnly = 1 in
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def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
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let AdditionalPredicates = [NotInMicroMips] in {
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// The 'pos + size' constraints are enforced by the code that lowers into
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// MipsISD::Ext.
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def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1,
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immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>,
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ISA_MIPS64R2;
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def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
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immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2;
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def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
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immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>,
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ISA_MIPS64R2;
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// The 'pos + size' constraints for code generation are enforced by the
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// code that lowers into MipsISD::Ext.
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// For assembly parsing, we alias dextu and dextm to dext, and match by
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// operand were possible then check the 'pos + size' in MipsAsmParser.
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// We override the generated decoder to enforce that dext always comes out
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// for dextm and dextu like binutils.
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let DecoderMethod = "DecodeDEXT" in {
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def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6,
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uimm5_plus1_report_uimm6, immZExt5, immZExt5Plus1,
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MipsExt>, EXT_FM<3>, ISA_MIPS64R2;
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def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
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immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2;
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def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
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immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>,
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ISA_MIPS64R2;
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}
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// The 'pos + size' constraints for code generation are enforced by the
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// code that lowers into MipsISD::Ins.
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// For assembly parsing, we alias dinsu and dinsm to dins, and match by
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@ -840,6 +846,12 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
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(DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
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uimm5_plus1:$size), 0>, ISA_MIPS64R2;
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def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
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(DEXTM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
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uimm5_plus33:$size), 0>, ISA_MIPS64R2;
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def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
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(DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
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uimm5_plus1:$size), 0>, ISA_MIPS64R2;
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// Two operand (implicit 0 selector) versions:
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def : MipsInstAlias<"dmtc0 $rt, $rd",
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@ -690,9 +690,14 @@ def ConstantUImm5Plus32NormalizeAsmOperandClass
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// We must also subtract 32 when we render the operand.
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let RenderMethod = "addConstantUImmOperands<5, 32, -32>";
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}
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def ConstantUImm5Plus1ReportUImm6AsmOperandClass
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: ConstantUImmAsmOperandClass<
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5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>{
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let Name = "ConstantUImm5_Plus1_Report_UImm6";
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}
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def ConstantUImm5Plus1AsmOperandClass
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: ConstantUImmAsmOperandClass<
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5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>;
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5, [ConstantUImm5Plus1ReportUImm6AsmOperandClass], 1>;
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def ConstantUImm5AsmOperandClass
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: ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>;
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def ConstantSImm5AsmOperandClass
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@ -799,6 +804,13 @@ def uimm5_plus1 : Operand<i32> {
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let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass;
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}
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def uimm5_plus1_report_uimm6 : Operand<i32> {
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let PrintMethod = "printUImm<6, 1>";
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let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>";
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let DecoderMethod = "DecodeUImmWithOffset<5, 1>";
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let ParserMatchClass = ConstantUImm5Plus1ReportUImm6AsmOperandClass;
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}
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def uimm5_plus32 : Operand<i32> {
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let PrintMethod = "printUImm<5, 32>";
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let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass;
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@ -38,8 +38,8 @@
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0x42 0x23 0x00 0x04 # CHECK: dahi $3, $3, 4
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0x42 0x03 0x00 0x04 # CHECK: dati $3, $3, 4
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0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
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0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39
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0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
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0x59 0x26 0x30 0xe4 # CHECK: dext $9, $6, 3, 39
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0x59 0x26 0x30 0xd4 # CHECK: dext $9, $6, 35, 7
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0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
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0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5
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0x58 0xa4 0x19 0x58 # CHECK: dmod $3, $4, $5
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@ -30,11 +30,9 @@
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daui $4, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
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dati $4, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
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dati $4, $5, 1 # CHECK: :[[@LINE]]:3: error: source and destination must match
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# FIXME: Check various 'pos + size' constraints on dext*
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dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
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dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
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dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
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dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
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dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
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dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
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dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
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@ -10,8 +10,8 @@
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# RUN: %s -o - | FileCheck --check-prefix=ASM %s
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dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
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dextu $2, $4, 34, 6 # OBJ: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
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dextm $2, $4, 5, 34 # OBJ: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
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dextu $2, $4, 34, 6 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
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dextm $2, $4, 5, 34 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
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dins $4, $5, 8, 10 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
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dinsm $4, $5, 30, 6 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 30, 6
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dinsu $4, $5, 40, 13 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
|
||||
@ -19,7 +19,14 @@
|
||||
dins $2, $4, 5, 10 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
|
||||
dins $2, $4, 34, 6 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
|
||||
dins $2, $4, 5, 34 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
|
||||
dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
|
||||
dext $2, $4, 34, 6 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
|
||||
dext $2, $4, 5, 34 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
|
||||
# check the edge values
|
||||
dins $3, $4, 31, 1 # ASM: dins $3, $4, 31, 1
|
||||
dins $3, $4, 31, 1 # ASM: dins $3, $4, 31, 1
|
||||
dins $3, $4, 31, 33 # ASM: dinsm $3, $4, 31, 33
|
||||
dins $3, $4, 32, 32 # ASM: dinsu $3, $4, 32, 32
|
||||
dext $3, $4, 31, 32 # ASM: dext $3, $4, 31, 32
|
||||
dext $3, $4, 31, 33 # ASM: dextm $3, $4, 31, 33
|
||||
dext $3, $4, 32, 32 # ASM: dextu $3, $4, 32, 32
|
||||
|
||||
|
||||
@ -10,28 +10,30 @@
|
||||
andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
|
||||
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
|
||||
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
|
||||
# FIXME: Check various 'pos + size' constraints on dext*
|
||||
dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
|
||||
dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
|
||||
dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
|
||||
dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
|
||||
dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
|
||||
dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
|
||||
dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
|
||||
dextm $2, $3, 32, 33 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
|
||||
dextm $2, $3, 1, 32 # CHECK: :[[@LINE]]:26: error: expected immediate in range 33 .. 64
|
||||
dextm $2, $3, 1, 65 # CHECK: :[[@LINE]]:26: error: expected immediate in range 33 .. 64
|
||||
dextm $3, $4, 31, 34 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
|
||||
dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
|
||||
dextu $2, $3, 32, 0 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32
|
||||
dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32
|
||||
dextu $3, $4, 33, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
# FIXME: Check size on dins*
|
||||
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
|
||||
dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
|
||||
dinsm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
|
||||
dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
|
||||
dinsm $4, $5, 31, 34 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
dinsu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
|
||||
dinsu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
|
||||
dinsu $4, $5, 33, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
drotr $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 6-bit unsigned immediate
|
||||
drotr $2, $3, 64 # CHECK: :[[@LINE]]:23: error: expected 6-bit unsigned immediate
|
||||
drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
|
||||
|
||||
@ -23,6 +23,10 @@ local_label:
|
||||
break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
|
||||
break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
|
||||
dati $2, $3, 1 # CHECK: :[[@LINE]]:9: error: source and destination must match
|
||||
dextm $3, $4, 31, 34 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
dextu $3, $4, 33, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
dinsm $4, $5, 31, 34 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
dinsu $4, $5, 33, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: size plus position are not in the range 33 .. 64
|
||||
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
|
||||
Loading…
Reference in New Issue
Block a user