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[SelectionDAG][X86] Support inline assembly returning an mmx register into a type with fewer than 64 bits.
It's possible to use the 'y' mmx constraint with a type narrower than 64-bits. This patch supports this by bitcasting the mmx type to 64-bits and then truncating to the desired type. There are probably other missing type combinations we need to support, but this is the case we have a bug report for. Fixes PR41748. Differential Revision: https://reviews.llvm.org/D61582 llvm-svn: 360069
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@ -322,6 +322,14 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
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return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
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}
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// Handle MMX to a narrower integer type by bitcasting MMX to integer and
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// then truncating.
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if (PartEVT == MVT::x86mmx && ValueVT.isInteger() &&
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ValueVT.bitsLT(PartEVT)) {
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Val = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Val);
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return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
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}
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report_fatal_error("Unknown mismatch in getCopyFromParts!");
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}
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15
test/CodeGen/X86/pr41748.ll
Normal file
15
test/CodeGen/X86/pr41748.ll
Normal file
@ -0,0 +1,15 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.14.0 -mattr=mmx | FileCheck %s
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define i32 @foo(i32 %a) {
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; CHECK-LABEL: foo:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: ## InlineAsm Start
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; CHECK-NEXT: movd %edi, %mm0
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; CHECK-NEXT: ## InlineAsm End
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; CHECK-NEXT: movd %mm0, %eax
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; CHECK-NEXT: retq
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entry:
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%0 = tail call i32 asm sideeffect "movd $1, $0", "=y,r,~{dirflag},~{fpsr},~{flags}"(i32 %a)
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ret i32 %0
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}
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