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[InstCombine] Add freezeAllUsesOfArgument to visitFreeze
In D106041, a freeze was added before the branch condition to solve the miscompilation problem of SimpleLoopUnswitch. However, I found that the added freeze disturbed other optimizations in the following situations. ``` arg.fr = freeze(arg) use(arg.fr) ... use(arg) ``` It is a problem that occurred when arg and arg.fr were recognized as different values. Therefore, changing to use arg.fr instead of arg throughout the function eliminates the above problem. Thus, I add a function that changes all uses of arg to freeze(arg) to visitFreeze of InstCombine. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D106233
This commit is contained in:
hyeongyu kim
parent
d4948ed188
commit
c8147441f9
@ -169,6 +169,7 @@ public:
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Instruction *visitLandingPadInst(LandingPadInst &LI);
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Instruction *visitVAEndInst(VAEndInst &I);
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Value *pushFreezeToPreventPoisonFromPropagating(FreezeInst &FI);
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bool freezeDominatedUses(FreezeInst &FI);
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Instruction *visitFreeze(FreezeInst &I);
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/// Specify what to return for unhandled instructions.
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@ -3605,6 +3605,22 @@ InstCombinerImpl::pushFreezeToPreventPoisonFromPropagating(FreezeInst &OrigFI) {
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return OrigOp;
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}
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bool InstCombinerImpl::freezeDominatedUses(FreezeInst &FI) {
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Value *Op = FI.getOperand(0);
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if (isa<Constant>(Op))
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return false;
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bool Changed = false;
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Op->replaceUsesWithIf(&FI, [&](Use &U) -> bool {
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bool Dominates = DT.dominates(&FI, U);
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Changed |= Dominates;
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return Dominates;
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});
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return Changed;
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}
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Instruction *InstCombinerImpl::visitFreeze(FreezeInst &I) {
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Value *Op0 = I.getOperand(0);
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@ -3648,6 +3664,10 @@ Instruction *InstCombinerImpl::visitFreeze(FreezeInst &I) {
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return replaceInstUsesWith(I, BestValue);
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}
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// Replace all dominated uses of Op to freeze(Op).
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if (freezeDominatedUses(I))
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return &I;
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return nullptr;
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}
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@ -135,3 +135,89 @@ define i32 @early_freeze_test3(i32 %v1) {
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%v4.fr = freeze i32 %v4
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ret i32 %v4.fr
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}
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; If replace all dominated uses of v to freeze(v).
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define void @freeze_dominated_uses_test1(i32 %v) {
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; CHECK-LABEL: @freeze_dominated_uses_test1(
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; CHECK-NEXT: [[V_FR:%.*]] = freeze i32 [[V:%.*]]
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; CHECK-NEXT: call void @use_i32(i32 [[V_FR]])
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; CHECK-NEXT: call void @use_i32(i32 [[V_FR]])
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; CHECK-NEXT: ret void
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;
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%v.fr = freeze i32 %v
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call void @use_i32(i32 %v)
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call void @use_i32(i32 %v.fr)
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ret void
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}
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define void @freeze_dominated_uses_test2(i32 %v) {
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; CHECK-LABEL: @freeze_dominated_uses_test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call void @use_i32(i32 [[V:%.*]])
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[V]], 0
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; CHECK-NEXT: br i1 [[COND]], label [[BB0:%.*]], label [[BB1:%.*]]
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; CHECK: bb0:
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; CHECK-NEXT: [[V_FR:%.*]] = freeze i32 [[V]]
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; CHECK-NEXT: call void @use_i32(i32 [[V_FR]])
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; CHECK-NEXT: call void @use_i32(i32 [[V_FR]])
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: call void @use_i32(i32 [[V]])
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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call void @use_i32(i32 %v)
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%cond = icmp eq i32 %v, 0
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br i1 %cond, label %bb0, label %bb1
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bb0:
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%v.fr = freeze i32 %v
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call void @use_i32(i32 %v.fr)
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call void @use_i32(i32 %v)
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br label %end
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bb1:
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call void @use_i32(i32 %v)
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br label %end
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end:
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ret void
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}
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; If there is a duplicate freeze, it will be removed.
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define void @freeze_dominated_uses_test3(i32 %v, i1 %cond) {
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; CHECK-LABEL: @freeze_dominated_uses_test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[V_FR1:%.*]] = freeze i32 [[V:%.*]]
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; CHECK-NEXT: call void @use_i32(i32 [[V_FR1]])
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; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB0:%.*]], label [[BB1:%.*]]
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; CHECK: bb0:
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; CHECK-NEXT: call void @use_i32(i32 [[V_FR1]])
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: call void @use_i32(i32 [[V_FR1]])
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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%v.fr1 = freeze i32 %v
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call void @use_i32(i32 %v.fr1)
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br i1 %cond, label %bb0, label %bb1
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bb0:
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%v.fr2 = freeze i32 %v
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call void @use_i32(i32 %v.fr2)
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br label %end
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bb1:
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call void @use_i32(i32 %v)
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br label %end
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end:
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ret void
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}
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@ -13,12 +13,11 @@ define float @test_merge_allof_v4sf(<4 x float> %t) {
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
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; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]]
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; CHECK: lor.lhs.false:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x float> [[T]]
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR6]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T_FR]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]]
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; CHECK-NEXT: br label [[RETURN]]
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@ -182,12 +181,11 @@ define float @test_separate_allof_v4sf(<4 x float> %t) {
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
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; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x float> [[T]]
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR6]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR]], <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T_FR]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]]
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; CHECK-NEXT: br label [[RETURN]]
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@ -357,14 +355,13 @@ define float @test_merge_allof_v4si(<4 x i32> %t) {
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
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; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]]
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; CHECK: lor.lhs.false:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]]
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; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR6]], <i32 255, i32 255, i32 255, i32 255>
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; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR]], <i32 255, i32 255, i32 255, i32 255>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1
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; CHECK-NEXT: br i1 [[TMP5]], label [[RETURN]], label [[IF_END:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T_FR]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0
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; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float
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; CHECK-NEXT: br label [[RETURN]]
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@ -515,12 +512,11 @@ define i32 @test_separate_allof_v4si(<4 x i32> %t) {
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
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; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[IF_END:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]]
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; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR6]], <i32 255, i32 255, i32 255, i32 255>
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; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR]], <i32 255, i32 255, i32 255, i32 255>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T_FR]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP5]], i32 0, i32 [[ADD]]
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; CHECK-NEXT: br label [[RETURN]]
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@ -594,12 +590,11 @@ define i32 @test_separate_anyof_v4si(<4 x i32> %t) {
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; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[RETURN:%.*]]
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; CHECK: if.end:
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; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[T_FR6]], <i32 255, i32 255, i32 255, i32 255>
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[T_FR]], <i32 255, i32 255, i32 255, i32 255>
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i1> [[TMP2]] to i4
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; CHECK-NEXT: [[DOTNOT7:%.*]] = icmp eq i4 [[TMP3]], 0
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw <4 x i32> [[SHIFT]], [[T]]
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; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw <4 x i32> [[SHIFT]], [[T_FR]]
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; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[DOTNOT7]], i32 [[ADD]], i32 0
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; CHECK-NEXT: br label [[RETURN]]
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