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[RISCV][NFC] Fix formatting

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This commit is contained in:
Jim Lin 2021-04-09 13:20:07 +08:00
parent 00f53956b9
commit c850cfde51
2 changed files with 151 additions and 150 deletions
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11
lib/Target/RISCV/RISCV.td
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@ -178,15 +178,16 @@ def FeatureStdExtZvlsseg
"'Zvlsseg' (Vector segment load/store instructions)", "'Zvlsseg' (Vector segment load/store instructions)",
[FeatureStdExtV]>; [FeatureStdExtV]>;
def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">, def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
AssemblerPredicate<(all_of FeatureStdExtZvlsseg), AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
"'Zvlsseg' (Vector segment load/store instructions)">; "'Zvlsseg' (Vector segment load/store instructions)">;
def FeatureExtZvamo def FeatureExtZvamo
: SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true", : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
"'Zvamo'(Vector AMO Operations)", "'Zvamo' (Vector AMO Operations)",
[FeatureStdExtV]>; [FeatureStdExtV]>;
def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">, def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
AssemblerPredicate<(all_of FeatureExtZvamo), AssemblerPredicate<(all_of FeatureExtZvamo),
"'Zvamo'(Vector AMO Operations)">; "'Zvamo' (Vector AMO Operations)">;
def Feature64Bit def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;

288
test/MC/RISCV/rvv/zvamo.s
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