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[PowerPC] Fix the check for the instruction using FRSP/XSRSP output register
When performing peephole optimization to simplify the code, after removing passed FPSP/XSRSP instruction we will set any uses of that FRSP/XSRSP to the source of the FRSP/XSRSP. We are finding the machine instruction using virtual register holding FRSP/XSRSP results by searching all following instructions and encountering an issue that the first use of the virtual register is a debug MI causing: 1. virtual register in the debug MI removed unexpectedly. 2. virtual register used in non-debug MI not replaced with the source of FRSP/XSRSP. which stays in a undef status. This patch fix the issue by only searching non-debug machine instruction using virtual register holding FRSP/XSRSP results when the vr only has one non debug usage. Differential Revisien: https://reviews.llvm.org/D94711 Reviewed by: nemanjai
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@ -712,7 +712,7 @@ bool PPCMIPeephole::simplifyCode(void) {
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Simplified = true;
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Simplified = true;
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Register ConvReg1 = RoundInstr->getOperand(1).getReg();
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Register ConvReg1 = RoundInstr->getOperand(1).getReg();
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Register FRSPDefines = RoundInstr->getOperand(0).getReg();
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Register FRSPDefines = RoundInstr->getOperand(0).getReg();
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MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
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MachineInstr &Use = *(MRI->use_instr_nodbg_begin(FRSPDefines));
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for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
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for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
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if (Use.getOperand(i).isReg() &&
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if (Use.getOperand(i).isReg() &&
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Use.getOperand(i).getReg() == FRSPDefines)
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Use.getOperand(i).getReg() == FRSPDefines)
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96
test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
Normal file
96
test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
Normal file
@ -0,0 +1,96 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; Function Attrs: nounwind
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define dso_local void @test(float* nocapture readonly %Fptr, <4 x float>* nocapture %Vptr) local_unnamed_addr #0 !dbg !10 {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3
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; CHECK-NEXT: #DEBUG_VALUE: test:Vptr <- $x4
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; CHECK-NEXT: addis 5, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: .loc 1 2 38 prologue_end
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; CHECK-NEXT: lfsx 0, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; CHECK-NEXT: .Ltmp1:
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; CHECK-NEXT: #DEBUG_VALUE: test:Fptr <- $x3
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; CHECK-NEXT: .loc 1 0 38 is_stmt 0
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; CHECK-NEXT: lfs 1, .LCPI0_0@toc@l(5)
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; CHECK-NEXT: lfd 2, .LCPI0_1@toc@l(3)
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; CHECK-NEXT: .loc 1 2 27
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; CHECK-NEXT: xssubdp 1, 1, 0
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; CHECK-NEXT: .loc 1 2 45
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; CHECK-NEXT: xsadddp 1, 1, 2
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; CHECK-NEXT: .Ltmp2:
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; CHECK-NEXT: #DEBUG_VALUE: test:Val <- undef
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; CHECK-NEXT: .loc 1 0 45
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; CHECK-NEXT: xxlxor 2, 2, 2
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; CHECK-NEXT: .loc 1 3 26 is_stmt 1
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; CHECK-NEXT: xxmrghd 0, 0, 2
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; CHECK-NEXT: xxmrghd 1, 2, 1
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; CHECK-NEXT: xvcvdpsp 34, 0
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; CHECK-NEXT: xvcvdpsp 35, 1
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; CHECK-NEXT: vmrgew 2, 2, 3
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; CHECK-NEXT: #DEBUG_VALUE: test:Vptr <- $x4
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; CHECK-NEXT: .loc 1 3 9 is_stmt 0
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; CHECK-NEXT: stvx 2, 0, 4
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; CHECK-NEXT: .loc 1 4 1 is_stmt 1
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; CHECK-NEXT: blr
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entry:
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call void @llvm.dbg.value(metadata float* %Fptr, metadata !19, metadata !DIExpression()), !dbg !22
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call void @llvm.dbg.value(metadata <4 x float>* %Vptr, metadata !20, metadata !DIExpression()), !dbg !22
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%0 = load float, float* %Fptr, align 4, !dbg !23, !tbaa !24
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%conv = fpext float %0 to double, !dbg !28
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%sub = fsub double 1.000000e+00, %conv, !dbg !29
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%sub1 = fadd double %sub, -4.300000e+00, !dbg !30
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%conv2 = fptrunc double %sub1 to float, !dbg !31
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call void @llvm.dbg.value(metadata float %conv2, metadata !21, metadata !DIExpression()), !dbg !22
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%vecinit4 = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float poison>, float %conv2, i32 0, !dbg !32
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%vecinit5 = insertelement <4 x float> %vecinit4, float %0, i32 3, !dbg !32
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store <4 x float> %vecinit5, <4 x float>* %Vptr, align 16, !dbg !33, !tbaa !34
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ret void, !dbg !35
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}
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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attributes #0 = { nounwind }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!6, !7, !8}
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!llvm.ident = !{!9}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, splitDebugInlining: false, nameTableKind: None)
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!1 = !DIFile(filename: "test.c", directory: "")
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!2 = !{}
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!3 = !{!4, !5}
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!4 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
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!5 = !DIBasicType(name: "double", size: 64, encoding: DW_ATE_float)
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!6 = !{i32 7, !"Dwarf Version", i32 4}
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!7 = !{i32 2, !"Debug Info Version", i32 3}
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!8 = !{i32 1, !"wchar_size", i32 4}
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!9 = !{!"clang version 12.0.0"}
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!10 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !11, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !18)
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!11 = !DISubroutineType(types: !12)
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!12 = !{null, !13, !14}
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!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64)
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!14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 64)
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!15 = !DICompositeType(tag: DW_TAG_array_type, baseType: !4, size: 128, flags: DIFlagVector, elements: !16)
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!16 = !{!17}
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!17 = !DISubrange(count: 4)
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!18 = !{!19, !20, !21}
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!19 = !DILocalVariable(name: "Fptr", arg: 1, scope: !10, file: !1, line: 1, type: !13)
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!20 = !DILocalVariable(name: "Vptr", arg: 2, scope: !10, file: !1, line: 1, type: !14)
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!21 = !DILocalVariable(name: "Val", scope: !10, file: !1, line: 2, type: !4)
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!22 = !DILocation(line: 0, scope: !10)
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!23 = !DILocation(line: 2, column: 38, scope: !10)
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!24 = !{!25, !25, i64 0}
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!25 = !{!"float", !26, i64 0}
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!26 = !{!"omnipotent char", !27, i64 0}
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!27 = !{!"Simple C/C++ TBAA"}
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!28 = !DILocation(line: 2, column: 29, scope: !10)
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!29 = !DILocation(line: 2, column: 27, scope: !10)
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!30 = !DILocation(line: 2, column: 45, scope: !10)
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!31 = !DILocation(line: 2, column: 15, scope: !10)
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!32 = !DILocation(line: 3, column: 26, scope: !10)
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!33 = !DILocation(line: 3, column: 9, scope: !10)
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!34 = !{!26, !26, i64 0}
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!35 = !DILocation(line: 4, column: 1, scope: !10)
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