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[Hexagon] Resize the mem operand when widening loads and stores

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This commit is contained in:
Krzysztof Parzyszek 2020-09-05 16:11:07 -05:00
parent 00ccf90843
commit c8b94c00f4
2 changed files with 39 additions and 2 deletions
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5
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -1704,18 +1704,19 @@ SDValue
HexagonTargetLowering::LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const {
const SDLoc &dl(Op);
unsigned HwLen = Subtarget.getVectorLength();
MachineFunction &MF = DAG.getMachineFunction();
auto *MaskN = cast<MaskedLoadStoreSDNode>(Op.getNode());
SDValue Mask = MaskN->getMask();
SDValue Chain = MaskN->getChain();
SDValue Base = MaskN->getBasePtr();
auto *MemOp = MaskN->getMemOperand();
auto *MemOp = MF.getMachineMemOperand(MaskN->getMemOperand(), 0, HwLen);
unsigned Opc = Op->getOpcode();
assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE);
if (Opc == ISD::MLOAD) {
MVT ValTy = ty(Op);
SDValue Load = DAG.getLoad(ValTy, dl, Chain, Base, MaskN->getMemOperand());
SDValue Load = DAG.getLoad(ValTy, dl, Chain, Base, MemOp);
SDValue Thru = cast<MaskedLoadSDNode>(MaskN)->getPassThru();
if (isUndef(Thru))
return Load;

36
test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll Normal file
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@ -0,0 +1,36 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check for successful compilation.
; CHECK-LABEL: f0:
; CHECK: dealloc_return
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define dso_local void @f0(i16* %a0) local_unnamed_addr #0 {
b0:
%v0 = getelementptr i16, i16* %a0, i32 8
%v1 = getelementptr i16, i16* %v0, i32 0
%v2 = icmp eq i32 0, 0
%v3 = insertelement <8 x i1> undef, i1 %v2, i64 0
%v4 = shufflevector <8 x i1> %v3, <8 x i1> undef, <8 x i32> zeroinitializer
%v5 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* nonnull undef, i32 4, <8 x i1> %v4, <8 x i32> undef)
%v6 = sub nsw <8 x i32> zeroinitializer, %v5
%v7 = add nsw <8 x i32> %v6, zeroinitializer
%v8 = add <8 x i32> zeroinitializer, %v7
%v9 = lshr <8 x i32> %v8, <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
%v10 = trunc <8 x i32> %v9 to <8 x i16>
%v11 = bitcast i16* %v1 to <8 x i16>*
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %v10, <8 x i16>* %v11, i32 2, <8 x i1> %v4)
ret void
}
; Function Attrs: argmemonly nounwind readonly willreturn
declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32 immarg, <8 x i1>, <8 x i32>) #1
; Function Attrs: argmemonly nounwind willreturn
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>) #2
attributes #0 = { "target-features"="+hvx-length64b,+hvxv65,+v65,-long-calls,-packets" }
attributes #1 = { argmemonly nounwind readonly willreturn }
attributes #2 = { argmemonly nounwind willreturn }