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Recommit r358211 "[X86] Use FILD/FIST to implement i64 atomic load on 32-bit targets with X87, but no SSE2"
With correct test checks this time. If we have X87, but not SSE2 we can atomicaly load an i64 value into the significand of an 80-bit extended precision x87 register using fild. We can then use a fist instruction to convert it back to an i64 integ This matches what gcc and icc do for this case and removes an existing FIXME. llvm-svn: 358214
This commit is contained in:
Craig Topper
parent
89eb2988e8
commit
c902f746a7
@ -25584,17 +25584,18 @@ bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
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// Note: this turns large loads into lock cmpxchg8b/16b.
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// TODO: In 32-bit mode, use MOVLPS when SSE1 is available?
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// TODO: In 32-bit mode, use FILD/FISTP when X87 is available?
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TargetLowering::AtomicExpansionKind
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X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
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Type *MemType = LI->getType();
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// If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled, we
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// can use movq to do the load.
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// can use movq to do the load. If we have X87 we can load into an 80-bit
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// X87 register and store it to a stack temporary.
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bool NoImplicitFloatOps =
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LI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat);
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if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
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!Subtarget.useSoftFloat() && !NoImplicitFloatOps && Subtarget.hasSSE2())
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!Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
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(Subtarget.hasSSE2() || Subtarget.hasX87()))
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return AtomicExpansionKind::None;
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return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
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@ -27440,23 +27441,57 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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bool NoImplicitFloatOps =
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DAG.getMachineFunction().getFunction().hasFnAttribute(
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Attribute::NoImplicitFloat);
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if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
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Subtarget.hasSSE2()) {
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if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps) {
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auto *Node = cast<AtomicSDNode>(N);
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// Use a VZEXT_LOAD which will be selected as MOVQ. Then extract the lower
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// 64-bits.
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SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
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SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
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SDValue Ld = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
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MVT::i64, Node->getMemOperand());
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SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld,
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DAG.getIntPtrConstant(0, dl));
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Results.push_back(Res);
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Results.push_back(Ld.getValue(1));
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return;
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if (Subtarget.hasSSE2()) {
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// Use a VZEXT_LOAD which will be selected as MOVQ. Then extract the
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// lower 64-bits.
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SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
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SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
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SDValue Ld = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
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MVT::i64, Node->getMemOperand());
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SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld,
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DAG.getIntPtrConstant(0, dl));
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Results.push_back(Res);
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Results.push_back(Ld.getValue(1));
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return;
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}
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if (Subtarget.hasX87()) {
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// First load this into an 80-bit X87 register. This will put the whole
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// integer into the significand.
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// FIXME: Do we need to glue? See FIXME comment in BuildFILD.
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SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other, MVT::Glue);
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SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
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SDValue Result = DAG.getMemIntrinsicNode(X86ISD::FILD_FLAG,
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dl, Tys, Ops, MVT::i64,
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Node->getMemOperand());
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SDValue Chain = Result.getValue(1);
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SDValue InFlag = Result.getValue(2);
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// Now store the X87 register to a stack temporary and convert to i64.
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// This store is not atomic and doesn't need to be.
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// FIXME: We don't need a stack temporary if the result of the load
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// is already being stored. We could just directly store there.
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SDValue StackPtr = DAG.CreateStackTemporary(MVT::i64);
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int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
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MachinePointerInfo MPI =
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MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
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SDValue StoreOps[] = { Chain, Result, StackPtr, InFlag };
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Chain = DAG.getMemIntrinsicNode(X86ISD::FIST, dl,
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DAG.getVTList(MVT::Other), StoreOps,
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MVT::i64, MPI, 0 /*Align*/,
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MachineMemOperand::MOStore);
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// Finally load the value back from the stack temporary and return it.
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// This load is not atomic and doesn't need to be.
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// This load will be further type legalized.
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Result = DAG.getLoad(MVT::i64, dl, Chain, StackPtr, MPI);
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Results.push_back(Result);
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Results.push_back(Result.getValue(1));
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return;
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}
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}
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// TODO: Use MOVLPS when SSE1 is available?
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// TODO: Use FILD/FISTP when X87 is available?
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// Delegate to generic TypeLegalization. Situations we can really handle
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// should have already been dealt with by AtomicExpandPass.cpp.
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break;
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@ -27649,6 +27684,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::FXOR: return "X86ISD::FXOR";
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case X86ISD::FILD: return "X86ISD::FILD";
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case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
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case X86ISD::FIST: return "X86ISD::FIST";
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case X86ISD::FP_TO_INT_IN_MEM: return "X86ISD::FP_TO_INT_IN_MEM";
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case X86ISD::FLD: return "X86ISD::FLD";
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case X86ISD::FST: return "X86ISD::FST";
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@ -608,16 +608,22 @@ namespace llvm {
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FILD,
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FILD_FLAG,
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/// This instruction implements a fp->int store from FP stack
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/// slots. This corresponds to the fist instruction. It takes a
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/// chain operand, value to store, address, and glue. The memory VT
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/// specifies the type to store as.
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FIST,
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/// This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, and ptr to load from. The memory VT specifies the type to
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/// load from.
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FLD,
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/// This instruction implements a truncating store to FP stack
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/// This instruction implements a truncating store from FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, and address. The memory VT specifies
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/// the type to store as.
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/// chain operand, value to store, address, and glue. The memory VT
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/// specifies the type to store as.
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FST,
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/// This instruction grabs the address of the next argument
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@ -21,6 +21,7 @@ def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>,
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def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>,
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SDTCisPtrTy<1>]>;
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def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
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def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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@ -35,6 +36,9 @@ def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
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[SDNPHasChain, SDNPOutGlue, SDNPMayLoad,
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SDNPMemOperand]>;
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def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist,
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[SDNPHasChain, SDNPInGlue, SDNPMayStore,
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SDNPMemOperand]>;
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def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>;
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def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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@ -79,6 +83,11 @@ def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def X86fist64 : PatFrag<(ops node:$val, node:$ptr),
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(X86fist node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr),
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(X86fp_to_mem node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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@ -760,6 +769,10 @@ def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
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// Used to conv. i64 to f64 since there isn't a SSE version.
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def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>;
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// Used to conv. between f80 and i64 for i64 atomic loads.
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def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>;
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def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>;
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// FP extensions map onto simple pseudo-value conversions if they are to/from
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// the FP stack.
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def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
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@ -77,14 +77,13 @@ define void @fadd_64r(double* %loc, double %val) nounwind {
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; X86-NOSSE-NEXT: pushl %ebx
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; X86-NOSSE-NEXT: pushl %esi
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; X86-NOSSE-NEXT: andl $-8, %esp
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; X86-NOSSE-NEXT: subl $16, %esp
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; X86-NOSSE-NEXT: subl $24, %esp
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; X86-NOSSE-NEXT: movl 8(%ebp), %esi
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; X86-NOSSE-NEXT: xorl %eax, %eax
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; X86-NOSSE-NEXT: xorl %edx, %edx
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; X86-NOSSE-NEXT: xorl %ecx, %ecx
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; X86-NOSSE-NEXT: xorl %ebx, %ebx
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; X86-NOSSE-NEXT: lock cmpxchg8b (%esi)
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; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: fildll (%esi)
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; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: faddl 12(%ebp)
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@ -112,14 +111,13 @@ define void @fadd_64r(double* %loc, double %val) nounwind {
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; X86-SSE1-NEXT: pushl %ebx
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; X86-SSE1-NEXT: pushl %esi
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $16, %esp
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; X86-SSE1-NEXT: subl $24, %esp
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; X86-SSE1-NEXT: movl 8(%ebp), %esi
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; X86-SSE1-NEXT: xorl %eax, %eax
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; X86-SSE1-NEXT: xorl %edx, %edx
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; X86-SSE1-NEXT: xorl %ecx, %ecx
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; X86-SSE1-NEXT: xorl %ebx, %ebx
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; X86-SSE1-NEXT: lock cmpxchg8b (%esi)
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; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fildll (%esi)
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: faddl 12(%ebp)
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@ -283,13 +281,12 @@ define void @fadd_64g() nounwind {
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; X86-NOSSE-NEXT: movl %esp, %ebp
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; X86-NOSSE-NEXT: pushl %ebx
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; X86-NOSSE-NEXT: andl $-8, %esp
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; X86-NOSSE-NEXT: subl $24, %esp
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; X86-NOSSE-NEXT: xorl %eax, %eax
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; X86-NOSSE-NEXT: xorl %edx, %edx
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; X86-NOSSE-NEXT: xorl %ecx, %ecx
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; X86-NOSSE-NEXT: xorl %ebx, %ebx
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; X86-NOSSE-NEXT: lock cmpxchg8b glob64
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; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: subl $32, %esp
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; X86-NOSSE-NEXT: fildll glob64
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; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: fld1
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; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
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@ -315,13 +312,12 @@ define void @fadd_64g() nounwind {
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; X86-SSE1-NEXT: movl %esp, %ebp
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; X86-SSE1-NEXT: pushl %ebx
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $24, %esp
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; X86-SSE1-NEXT: xorl %eax, %eax
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; X86-SSE1-NEXT: xorl %edx, %edx
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; X86-SSE1-NEXT: xorl %ecx, %ecx
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; X86-SSE1-NEXT: xorl %ebx, %ebx
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; X86-SSE1-NEXT: lock cmpxchg8b glob64
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; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: subl $32, %esp
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; X86-SSE1-NEXT: fildll glob64
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fld1
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; X86-SSE1-NEXT: faddl {{[0-9]+}}(%esp)
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@ -484,13 +480,12 @@ define void @fadd_64imm() nounwind {
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; X86-NOSSE-NEXT: movl %esp, %ebp
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; X86-NOSSE-NEXT: pushl %ebx
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; X86-NOSSE-NEXT: andl $-8, %esp
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; X86-NOSSE-NEXT: subl $24, %esp
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; X86-NOSSE-NEXT: xorl %eax, %eax
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; X86-NOSSE-NEXT: xorl %edx, %edx
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; X86-NOSSE-NEXT: xorl %ecx, %ecx
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; X86-NOSSE-NEXT: xorl %ebx, %ebx
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; X86-NOSSE-NEXT: lock cmpxchg8b -559038737
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; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: subl $32, %esp
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; X86-NOSSE-NEXT: fildll -559038737
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; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: fld1
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; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
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@ -516,13 +511,12 @@ define void @fadd_64imm() nounwind {
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; X86-SSE1-NEXT: movl %esp, %ebp
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; X86-SSE1-NEXT: pushl %ebx
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $24, %esp
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; X86-SSE1-NEXT: xorl %eax, %eax
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; X86-SSE1-NEXT: xorl %edx, %edx
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; X86-SSE1-NEXT: xorl %ecx, %ecx
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; X86-SSE1-NEXT: xorl %ebx, %ebx
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; X86-SSE1-NEXT: lock cmpxchg8b -559038737
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; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: subl $32, %esp
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; X86-SSE1-NEXT: fildll -559038737
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fld1
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; X86-SSE1-NEXT: faddl {{[0-9]+}}(%esp)
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@ -691,13 +685,12 @@ define void @fadd_64stack() nounwind {
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; X86-NOSSE-NEXT: movl %esp, %ebp
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; X86-NOSSE-NEXT: pushl %ebx
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; X86-NOSSE-NEXT: andl $-8, %esp
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; X86-NOSSE-NEXT: subl $32, %esp
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; X86-NOSSE-NEXT: xorl %eax, %eax
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; X86-NOSSE-NEXT: xorl %edx, %edx
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; X86-NOSSE-NEXT: xorl %ecx, %ecx
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; X86-NOSSE-NEXT: xorl %ebx, %ebx
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; X86-NOSSE-NEXT: lock cmpxchg8b (%esp)
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; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: subl $40, %esp
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; X86-NOSSE-NEXT: fildll (%esp)
|
||||
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: fld1
|
||||
; X86-NOSSE-NEXT: faddl {{[0-9]+}}(%esp)
|
||||
@ -723,13 +716,12 @@ define void @fadd_64stack() nounwind {
|
||||
; X86-SSE1-NEXT: movl %esp, %ebp
|
||||
; X86-SSE1-NEXT: pushl %ebx
|
||||
; X86-SSE1-NEXT: andl $-8, %esp
|
||||
; X86-SSE1-NEXT: subl $32, %esp
|
||||
; X86-SSE1-NEXT: xorl %eax, %eax
|
||||
; X86-SSE1-NEXT: xorl %edx, %edx
|
||||
; X86-SSE1-NEXT: xorl %ecx, %ecx
|
||||
; X86-SSE1-NEXT: xorl %ebx, %ebx
|
||||
; X86-SSE1-NEXT: lock cmpxchg8b (%esp)
|
||||
; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: subl $40, %esp
|
||||
; X86-SSE1-NEXT: fildll (%esp)
|
||||
; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: fld1
|
||||
; X86-SSE1-NEXT: faddl {{[0-9]+}}(%esp)
|
||||
@ -831,15 +823,14 @@ define void @fadd_array(i64* %arg, double %arg1, i64 %arg2) nounwind {
|
||||
; X86-NOSSE-NEXT: pushl %edi
|
||||
; X86-NOSSE-NEXT: pushl %esi
|
||||
; X86-NOSSE-NEXT: andl $-8, %esp
|
||||
; X86-NOSSE-NEXT: subl $24, %esp
|
||||
; X86-NOSSE-NEXT: subl $32, %esp
|
||||
; X86-NOSSE-NEXT: movl 20(%ebp), %esi
|
||||
; X86-NOSSE-NEXT: movl 8(%ebp), %edi
|
||||
; X86-NOSSE-NEXT: xorl %eax, %eax
|
||||
; X86-NOSSE-NEXT: xorl %edx, %edx
|
||||
; X86-NOSSE-NEXT: xorl %ecx, %ecx
|
||||
; X86-NOSSE-NEXT: xorl %ebx, %ebx
|
||||
; X86-NOSSE-NEXT: lock cmpxchg8b (%edi,%esi,8)
|
||||
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: fildll (%edi,%esi,8)
|
||||
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl %eax, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: faddl 12(%ebp)
|
||||
@ -869,15 +860,14 @@ define void @fadd_array(i64* %arg, double %arg1, i64 %arg2) nounwind {
|
||||
; X86-SSE1-NEXT: pushl %edi
|
||||
; X86-SSE1-NEXT: pushl %esi
|
||||
; X86-SSE1-NEXT: andl $-8, %esp
|
||||
; X86-SSE1-NEXT: subl $24, %esp
|
||||
; X86-SSE1-NEXT: subl $32, %esp
|
||||
; X86-SSE1-NEXT: movl 20(%ebp), %esi
|
||||
; X86-SSE1-NEXT: movl 8(%ebp), %edi
|
||||
; X86-SSE1-NEXT: xorl %eax, %eax
|
||||
; X86-SSE1-NEXT: xorl %edx, %edx
|
||||
; X86-SSE1-NEXT: xorl %ecx, %ecx
|
||||
; X86-SSE1-NEXT: xorl %ebx, %ebx
|
||||
; X86-SSE1-NEXT: lock cmpxchg8b (%edi,%esi,8)
|
||||
; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: fildll (%edi,%esi,8)
|
||||
; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: fldl {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: faddl 12(%ebp)
|
||||
|
||||
@ -45,22 +45,21 @@ define i64 @test2(i64* %ptr) {
|
||||
;
|
||||
; NOSSE-LABEL: test2:
|
||||
; NOSSE: # %bb.0:
|
||||
; NOSSE-NEXT: pushl %ebx
|
||||
; NOSSE-NEXT: pushl %ebp
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; NOSSE-NEXT: pushl %esi
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 12
|
||||
; NOSSE-NEXT: .cfi_offset %esi, -12
|
||||
; NOSSE-NEXT: .cfi_offset %ebx, -8
|
||||
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; NOSSE-NEXT: xorl %eax, %eax
|
||||
; NOSSE-NEXT: xorl %edx, %edx
|
||||
; NOSSE-NEXT: xorl %ecx, %ecx
|
||||
; NOSSE-NEXT: xorl %ebx, %ebx
|
||||
; NOSSE-NEXT: lock cmpxchg8b (%esi)
|
||||
; NOSSE-NEXT: popl %esi
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; NOSSE-NEXT: popl %ebx
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 4
|
||||
; NOSSE-NEXT: .cfi_offset %ebp, -8
|
||||
; NOSSE-NEXT: movl %esp, %ebp
|
||||
; NOSSE-NEXT: .cfi_def_cfa_register %ebp
|
||||
; NOSSE-NEXT: andl $-8, %esp
|
||||
; NOSSE-NEXT: subl $8, %esp
|
||||
; NOSSE-NEXT: movl 8(%ebp), %eax
|
||||
; NOSSE-NEXT: fildll (%eax)
|
||||
; NOSSE-NEXT: fistpll (%esp)
|
||||
; NOSSE-NEXT: movl (%esp), %eax
|
||||
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
|
||||
; NOSSE-NEXT: movl %ebp, %esp
|
||||
; NOSSE-NEXT: popl %ebp
|
||||
; NOSSE-NEXT: .cfi_def_cfa %esp, 4
|
||||
; NOSSE-NEXT: retl
|
||||
%val = load atomic i64, i64* %ptr seq_cst, align 8
|
||||
ret i64 %val
|
||||
@ -102,22 +101,21 @@ define i64 @test4(i64* %ptr) {
|
||||
;
|
||||
; NOSSE-LABEL: test4:
|
||||
; NOSSE: # %bb.0:
|
||||
; NOSSE-NEXT: pushl %ebx
|
||||
; NOSSE-NEXT: pushl %ebp
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; NOSSE-NEXT: pushl %esi
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 12
|
||||
; NOSSE-NEXT: .cfi_offset %esi, -12
|
||||
; NOSSE-NEXT: .cfi_offset %ebx, -8
|
||||
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; NOSSE-NEXT: xorl %eax, %eax
|
||||
; NOSSE-NEXT: xorl %edx, %edx
|
||||
; NOSSE-NEXT: xorl %ecx, %ecx
|
||||
; NOSSE-NEXT: xorl %ebx, %ebx
|
||||
; NOSSE-NEXT: lock cmpxchg8b (%esi)
|
||||
; NOSSE-NEXT: popl %esi
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; NOSSE-NEXT: popl %ebx
|
||||
; NOSSE-NEXT: .cfi_def_cfa_offset 4
|
||||
; NOSSE-NEXT: .cfi_offset %ebp, -8
|
||||
; NOSSE-NEXT: movl %esp, %ebp
|
||||
; NOSSE-NEXT: .cfi_def_cfa_register %ebp
|
||||
; NOSSE-NEXT: andl $-8, %esp
|
||||
; NOSSE-NEXT: subl $8, %esp
|
||||
; NOSSE-NEXT: movl 8(%ebp), %eax
|
||||
; NOSSE-NEXT: fildll (%eax)
|
||||
; NOSSE-NEXT: fistpll (%esp)
|
||||
; NOSSE-NEXT: movl (%esp), %eax
|
||||
; NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
|
||||
; NOSSE-NEXT: movl %ebp, %esp
|
||||
; NOSSE-NEXT: popl %ebp
|
||||
; NOSSE-NEXT: .cfi_def_cfa %esp, 4
|
||||
; NOSSE-NEXT: retl
|
||||
%val = load atomic volatile i64, i64* %ptr seq_cst, align 8
|
||||
ret i64 %val
|
||||
|
||||
@ -331,20 +331,22 @@ define void @add_64i(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: add_64i:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: addl $2, %ebx
|
||||
; X32-NEXT: adcl $0, %ecx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
@ -355,10 +357,11 @@ define void @add_64i(i64* %p) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB14_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'addq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -375,22 +378,24 @@ define void @add_64r(i64* %p, i64 %v) {
|
||||
;
|
||||
; X32-LABEL: add_64r:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: addl {{[0-9]+}}(%esp), %ebx
|
||||
; X32-NEXT: adcl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: addl 12(%ebp), %ebx
|
||||
; X32-NEXT: adcl 16(%ebp), %ecx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
; X32-NEXT: .p2align 4, 0x90
|
||||
@ -399,10 +404,11 @@ define void @add_64r(i64* %p, i64 %v) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB15_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'addq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -565,22 +571,24 @@ define void @sub_64r(i64* %p, i64 %v) {
|
||||
;
|
||||
; X32-LABEL: sub_64r:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: subl {{[0-9]+}}(%esp), %ebx
|
||||
; X32-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: subl 12(%ebp), %ebx
|
||||
; X32-NEXT: sbbl 16(%ebp), %ecx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
; X32-NEXT: .p2align 4, 0x90
|
||||
@ -589,10 +597,11 @@ define void @sub_64r(i64* %p, i64 %v) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB23_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'subq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -737,19 +746,21 @@ define void @and_64i(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: and_64i:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: andl $2, %ebx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
@ -760,10 +771,11 @@ define void @and_64i(i64* %p) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB31_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'andq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -780,22 +792,24 @@ define void @and_64r(i64* %p, i64 %v) {
|
||||
;
|
||||
; X32-LABEL: and_64r:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: andl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: andl {{[0-9]+}}(%esp), %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: andl 16(%ebp), %ecx
|
||||
; X32-NEXT: andl 12(%ebp), %ebx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
; X32-NEXT: .p2align 4, 0x90
|
||||
@ -804,10 +818,11 @@ define void @and_64r(i64* %p, i64 %v) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB32_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'andq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -973,20 +988,22 @@ define void @or_64i(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: or_64i:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: orl $2, %ebx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
@ -996,10 +1013,11 @@ define void @or_64i(i64* %p) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB41_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'orq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -1016,22 +1034,24 @@ define void @or_64r(i64* %p, i64 %v) {
|
||||
;
|
||||
; X32-LABEL: or_64r:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: orl {{[0-9]+}}(%esp), %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: orl 16(%ebp), %ecx
|
||||
; X32-NEXT: orl 12(%ebp), %ebx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
; X32-NEXT: .p2align 4, 0x90
|
||||
@ -1040,10 +1060,11 @@ define void @or_64r(i64* %p, i64 %v) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB42_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'orq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -1209,20 +1230,22 @@ define void @xor_64i(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: xor_64i:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: xorl $2, %ebx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
@ -1232,10 +1255,11 @@ define void @xor_64i(i64* %p) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB51_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'xorq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -1252,22 +1276,24 @@ define void @xor_64r(i64* %p, i64 %v) {
|
||||
;
|
||||
; X32-LABEL: xor_64r:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: xorl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: xorl {{[0-9]+}}(%esp), %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: xorl 16(%ebp), %ecx
|
||||
; X32-NEXT: xorl 12(%ebp), %ebx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
; X32-NEXT: .p2align 4, 0x90
|
||||
@ -1276,10 +1302,11 @@ define void @xor_64r(i64* %p, i64 %v) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB52_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'xorq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -1406,20 +1433,22 @@ define void @inc_64(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: inc_64:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: addl $1, %ebx
|
||||
; X32-NEXT: adcl $0, %ecx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
@ -1430,10 +1459,11 @@ define void @inc_64(i64* %p) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB58_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; SLOW_INC-LABEL: inc_64:
|
||||
@ -1551,20 +1581,22 @@ define void @dec_64(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: dec_64:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: addl $-1, %ebx
|
||||
; X32-NEXT: adcl $-1, %ecx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
@ -1575,10 +1607,11 @@ define void @dec_64(i64* %p) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB63_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; SLOW_INC-LABEL: dec_64:
|
||||
@ -1681,20 +1714,22 @@ define void @not_64(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: not_64:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %esi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: movl %edx, %ecx
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: movl (%esp), %ebx
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: notl %ecx
|
||||
; X32-NEXT: notl %ebx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
@ -1705,10 +1740,11 @@ define void @not_64(i64* %p) {
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB68_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do not check X86-32 as it cannot do 'notq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
@ -1803,40 +1839,37 @@ define void @neg_64(i64* %p) {
|
||||
;
|
||||
; X32-LABEL: neg_64:
|
||||
; X32: # %bb.0:
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: pushl %edi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: pushl %ebx
|
||||
; X32-NEXT: pushl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 16
|
||||
; X32-NEXT: andl $-8, %esp
|
||||
; X32-NEXT: subl $8, %esp
|
||||
; X32-NEXT: .cfi_offset %esi, -16
|
||||
; X32-NEXT: .cfi_offset %edi, -12
|
||||
; X32-NEXT: .cfi_offset %ebx, -8
|
||||
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
|
||||
; X32-NEXT: xorl %esi, %esi
|
||||
; X32-NEXT: xorl %eax, %eax
|
||||
; X32-NEXT: xorl %edx, %edx
|
||||
; X32-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-NEXT: movl 8(%ebp), %esi
|
||||
; X32-NEXT: fildll (%esi)
|
||||
; X32-NEXT: fistpll (%esp)
|
||||
; X32-NEXT: xorl %ecx, %ecx
|
||||
; X32-NEXT: xorl %ebx, %ebx
|
||||
; X32-NEXT: lock cmpxchg8b (%edi)
|
||||
; X32-NEXT: movl %eax, %ebx
|
||||
; X32-NEXT: negl %ebx
|
||||
; X32-NEXT: sbbl %edx, %esi
|
||||
; X32-NEXT: movl (%edi), %eax
|
||||
; X32-NEXT: movl 4(%edi), %edx
|
||||
; X32-NEXT: subl (%esp), %ebx
|
||||
; X32-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
|
||||
; X32-NEXT: movl (%esi), %eax
|
||||
; X32-NEXT: movl 4(%esi), %edx
|
||||
; X32-NEXT: .p2align 4, 0x90
|
||||
; X32-NEXT: .LBB73_1: # %atomicrmw.start
|
||||
; X32-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; X32-NEXT: movl %esi, %ecx
|
||||
; X32-NEXT: lock cmpxchg8b (%edi)
|
||||
; X32-NEXT: lock cmpxchg8b (%esi)
|
||||
; X32-NEXT: jne .LBB73_1
|
||||
; X32-NEXT: # %bb.2: # %atomicrmw.end
|
||||
; X32-NEXT: leal -8(%ebp), %esp
|
||||
; X32-NEXT: popl %esi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-NEXT: popl %edi
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: popl %ebx
|
||||
; X32-NEXT: .cfi_def_cfa_offset 4
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: .cfi_def_cfa %esp, 4
|
||||
; X32-NEXT: retl
|
||||
; We do neg check X86-32 as it canneg do 'negq'.
|
||||
%1 = load atomic i64, i64* %p acquire, align 8
|
||||
|
||||
@ -397,28 +397,17 @@ define float @load_float(float* %fptr) {
|
||||
define double @load_double(double* %fptr) {
|
||||
; X86-SSE1-LABEL: load_double:
|
||||
; X86-SSE1: # %bb.0:
|
||||
; X86-SSE1-NEXT: pushl %ebx
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-SSE1-NEXT: pushl %esi
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-SSE1-NEXT: subl $12, %esp
|
||||
; X86-SSE1-NEXT: subl $20, %esp
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 24
|
||||
; X86-SSE1-NEXT: .cfi_offset %esi, -12
|
||||
; X86-SSE1-NEXT: .cfi_offset %ebx, -8
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X86-SSE1-NEXT: xorl %eax, %eax
|
||||
; X86-SSE1-NEXT: xorl %edx, %edx
|
||||
; X86-SSE1-NEXT: xorl %ecx, %ecx
|
||||
; X86-SSE1-NEXT: xorl %ebx, %ebx
|
||||
; X86-SSE1-NEXT: lock cmpxchg8b (%esi)
|
||||
; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE1-NEXT: fildll (%eax)
|
||||
; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl %eax, (%esp)
|
||||
; X86-SSE1-NEXT: fldl (%esp)
|
||||
; X86-SSE1-NEXT: addl $12, %esp
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-SSE1-NEXT: popl %esi
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-SSE1-NEXT: popl %ebx
|
||||
; X86-SSE1-NEXT: addl $20, %esp
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 4
|
||||
; X86-SSE1-NEXT: retl
|
||||
;
|
||||
@ -448,28 +437,17 @@ define double @load_double(double* %fptr) {
|
||||
;
|
||||
; X86-NOSSE-LABEL: load_double:
|
||||
; X86-NOSSE: # %bb.0:
|
||||
; X86-NOSSE-NEXT: pushl %ebx
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-NOSSE-NEXT: pushl %esi
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-NOSSE-NEXT: subl $12, %esp
|
||||
; X86-NOSSE-NEXT: subl $20, %esp
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 24
|
||||
; X86-NOSSE-NEXT: .cfi_offset %esi, -12
|
||||
; X86-NOSSE-NEXT: .cfi_offset %ebx, -8
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X86-NOSSE-NEXT: xorl %eax, %eax
|
||||
; X86-NOSSE-NEXT: xorl %edx, %edx
|
||||
; X86-NOSSE-NEXT: xorl %ecx, %ecx
|
||||
; X86-NOSSE-NEXT: xorl %ebx, %ebx
|
||||
; X86-NOSSE-NEXT: lock cmpxchg8b (%esi)
|
||||
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NOSSE-NEXT: fildll (%eax)
|
||||
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl %eax, (%esp)
|
||||
; X86-NOSSE-NEXT: fldl (%esp)
|
||||
; X86-NOSSE-NEXT: addl $12, %esp
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-NOSSE-NEXT: popl %esi
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-NOSSE-NEXT: popl %ebx
|
||||
; X86-NOSSE-NEXT: addl $20, %esp
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4
|
||||
; X86-NOSSE-NEXT: retl
|
||||
;
|
||||
@ -776,28 +754,17 @@ define float @load_float_seq_cst(float* %fptr) {
|
||||
define double @load_double_seq_cst(double* %fptr) {
|
||||
; X86-SSE1-LABEL: load_double_seq_cst:
|
||||
; X86-SSE1: # %bb.0:
|
||||
; X86-SSE1-NEXT: pushl %ebx
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-SSE1-NEXT: pushl %esi
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-SSE1-NEXT: subl $12, %esp
|
||||
; X86-SSE1-NEXT: subl $20, %esp
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 24
|
||||
; X86-SSE1-NEXT: .cfi_offset %esi, -12
|
||||
; X86-SSE1-NEXT: .cfi_offset %ebx, -8
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X86-SSE1-NEXT: xorl %eax, %eax
|
||||
; X86-SSE1-NEXT: xorl %edx, %edx
|
||||
; X86-SSE1-NEXT: xorl %ecx, %ecx
|
||||
; X86-SSE1-NEXT: xorl %ebx, %ebx
|
||||
; X86-SSE1-NEXT: lock cmpxchg8b (%esi)
|
||||
; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE1-NEXT: fildll (%eax)
|
||||
; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-SSE1-NEXT: movl %eax, (%esp)
|
||||
; X86-SSE1-NEXT: fldl (%esp)
|
||||
; X86-SSE1-NEXT: addl $12, %esp
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-SSE1-NEXT: popl %esi
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-SSE1-NEXT: popl %ebx
|
||||
; X86-SSE1-NEXT: addl $20, %esp
|
||||
; X86-SSE1-NEXT: .cfi_def_cfa_offset 4
|
||||
; X86-SSE1-NEXT: retl
|
||||
;
|
||||
@ -827,28 +794,17 @@ define double @load_double_seq_cst(double* %fptr) {
|
||||
;
|
||||
; X86-NOSSE-LABEL: load_double_seq_cst:
|
||||
; X86-NOSSE: # %bb.0:
|
||||
; X86-NOSSE-NEXT: pushl %ebx
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-NOSSE-NEXT: pushl %esi
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-NOSSE-NEXT: subl $12, %esp
|
||||
; X86-NOSSE-NEXT: subl $20, %esp
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 24
|
||||
; X86-NOSSE-NEXT: .cfi_offset %esi, -12
|
||||
; X86-NOSSE-NEXT: .cfi_offset %ebx, -8
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X86-NOSSE-NEXT: xorl %eax, %eax
|
||||
; X86-NOSSE-NEXT: xorl %edx, %edx
|
||||
; X86-NOSSE-NEXT: xorl %ecx, %ecx
|
||||
; X86-NOSSE-NEXT: xorl %ebx, %ebx
|
||||
; X86-NOSSE-NEXT: lock cmpxchg8b (%esi)
|
||||
; X86-NOSSE-NEXT: movl %edx, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NOSSE-NEXT: fildll (%eax)
|
||||
; X86-NOSSE-NEXT: fistpll {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NOSSE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
|
||||
; X86-NOSSE-NEXT: movl %eax, (%esp)
|
||||
; X86-NOSSE-NEXT: fldl (%esp)
|
||||
; X86-NOSSE-NEXT: addl $12, %esp
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 12
|
||||
; X86-NOSSE-NEXT: popl %esi
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
|
||||
; X86-NOSSE-NEXT: popl %ebx
|
||||
; X86-NOSSE-NEXT: addl $20, %esp
|
||||
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4
|
||||
; X86-NOSSE-NEXT: retl
|
||||
;
|
||||
|
||||
@ -49,4 +49,4 @@ k.end: ; preds = %entry
|
||||
|
||||
declare i32 @m()
|
||||
|
||||
attributes #0 = { "no-frame-pointer-elim-non-leaf" }
|
||||
attributes #0 = { noimplicitfloat "no-frame-pointer-elim-non-leaf" }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user