RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Code Issues Projects Releases Wiki Activity

R600/SI: add srl/sha patterns for SI

Browse Source 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 178125
This commit is contained in:
Christian Konig 2013-03-27 09:12:44 +00:00
parent e0c66d8042
commit c90c1dabd1
3 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/R600/SIInstructions.td
View File

@ -850,9 +850,13 @@ defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>;
} // End isCommutable = 1
defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>;
defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
[(set VReg_32:$dst, (srl VSrc_32:$src0, (i32 VReg_32:$src1)))]
>;
defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", []>;
defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>;
defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
[(set VReg_32:$dst, (sra VSrc_32:$src0, (i32 VReg_32:$src1)))]
>;
defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", []>;
defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
[(set VReg_32:$dst, (shl VSrc_32:$src0, (i32 VReg_32:$src1)))]

14
test/CodeGen/R600/lshl.ll Normal file
View File

@ -0,0 +1,14 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;CHECK: V_LSHL_B32_e64 VGPR0, VGPR0, 1, 0, 0, 0, 0
define void @test(i32 %p) {
%i = mul i32 %p, 2
%r = bitcast i32 %i to float
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)
ret void
}
declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

14
test/CodeGen/R600/lshr.ll Normal file
View File

@ -0,0 +1,14 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;CHECK: V_LSHR_B32_e64 VGPR0, VGPR0, 1, 0, 0, 0, 0
define void @test(i32 %p) {
%i = udiv i32 %p, 2
%r = bitcast i32 %i to float
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)
ret void
}
declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)