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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU/GlobalISel: Select G_PHI
llvm-svn: 364805
This commit is contained in:
Matt Arsenault
parent
b5b924114f
commit
c951a718b7
@ -133,6 +133,44 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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return true;
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}
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bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const Register DefReg = I.getOperand(0).getReg();
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const LLT DefTy = MRI.getType(DefReg);
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// TODO: Verify this doesn't have insane operands (i.e. VGPR to SGPR copy)
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const RegClassOrRegBank &RegClassOrBank =
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MRI.getRegClassOrRegBank(DefReg);
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const TargetRegisterClass *DefRC
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= RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
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if (!DefRC) {
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if (!DefTy.isValid()) {
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LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
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return false;
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}
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const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
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if (RB.getID() == AMDGPU::SCCRegBankID) {
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LLVM_DEBUG(dbgs() << "illegal scc phi\n");
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return false;
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}
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DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, MRI);
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if (!DefRC) {
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LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
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return false;
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}
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}
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I.setDesc(TII.get(TargetOpcode::PHI));
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return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
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}
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MachineOperand
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AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
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unsigned SubIdx) const {
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@ -1048,6 +1086,8 @@ bool AMDGPUInstructionSelector::selectG_FRAME_INDEX(MachineInstr &I) const {
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bool AMDGPUInstructionSelector::select(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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if (I.isPHI())
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return selectPHI(I);
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if (!isPreISelGenericOpcode(I.getOpcode())) {
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if (I.isCopy())
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@ -67,6 +67,7 @@ private:
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MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
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bool selectCOPY(MachineInstr &I) const;
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bool selectPHI(MachineInstr &I) const;
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bool selectG_TRUNC(MachineInstr &I) const;
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bool selectG_SZA_EXT(MachineInstr &I) const;
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bool selectG_CONSTANT(MachineInstr &I) const;
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31
test/CodeGen/AMDGPU/GlobalISel/inst-select-phi-invalid.mir
Normal file
31
test/CodeGen/AMDGPU/GlobalISel/inst-select-phi-invalid.mir
Normal file
@ -0,0 +1,31 @@
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# RUN: llc -march=amdgcn -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=ERR
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# ERR: remark: <unknown>:0:0: cannot select: %7:scc(s1) = G_PHI %4:scc(s1), %bb.0, %6:scc(s1), %bb.1 (in function: g_phi_scc_s1_sbranch)
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---
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name: g_phi_scc_s1_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:scc(s1) = G_ICMP intpred(eq), %0, %3
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%5:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %5(s1), %bb.1
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G_BR %bb.2
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bb.1:
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%6:scc(s1) = G_ICMP intpred(eq), %1, %3
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G_BR %bb.2
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bb.2:
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%7:scc(s1) = G_PHI %4, %bb.0, %6, %bb.1
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S_SETPC_B64 undef $sgpr30_sgpr31, implicit %7
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...
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385
test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
Normal file
385
test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
Normal file
@ -0,0 +1,385 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN
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---
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name: g_phi_s32_ss_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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; GCN-LABEL: name: g_phi_s32_ss_sbranch
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: liveins: $sgpr0, $sgpr1, $sgpr2
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: S_BRANCH %bb.2
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; GCN: bb.2:
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; GCN: [[PHI:%[0-9]+]]:sreg_32_xm0 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
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; GCN: $sgpr0 = COPY [[PHI]]
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; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %4(s1), %bb.1
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G_BR %bb.2
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bb.1:
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%5:sgpr(s32) = COPY %1
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G_BR %bb.2
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bb.2:
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%6:sgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
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$sgpr0 = COPY %6
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: g_phi_s32_vv_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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; GCN-LABEL: name: g_phi_s32_vv_sbranch
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: liveins: $vgpr0, $vgpr1, $sgpr2
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY1]]
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; GCN: S_BRANCH %bb.2
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; GCN: bb.2:
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; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
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; GCN: $vgpr0 = COPY [[PHI]]
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; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr2
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %4(s1), %bb.1
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G_BR %bb.2
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bb.1:
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%5:sgpr(s32) = COPY %1
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G_BR %bb.2
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bb.2:
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%6:vgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
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$vgpr0 = COPY %6(s32)
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: g_phi_s32_sv_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %4(s1), %bb.1
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G_BR %bb.2
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bb.1:
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%5:vgpr(s32) = COPY %1
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G_BR %bb.2
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bb.2:
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%6:vgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
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$vgpr0 = COPY %6
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: g_phi_s32_vs_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $sgpr1
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:sgpr(s32) = COPY $sgpr1
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %4(s1), %bb.1
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G_BR %bb.2
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bb.1:
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%5:vgpr(s32) = COPY %1
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G_BR %bb.2
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bb.2:
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%6:vgpr(s32) = G_PHI %0(s32), %bb.0, %5(s32), %bb.1
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$vgpr0 = COPY %6
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: g_phi_s64_ss_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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; GCN-LABEL: name: g_phi_s64_ss_sbranch
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: S_BRANCH %bb.2
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; GCN: bb.2:
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; GCN: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
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; GCN: $sgpr0_sgpr1 = COPY [[PHI]]
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; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = COPY $sgpr2_sgpr3
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%2:sgpr(s32) = COPY $sgpr4
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %4(s1), %bb.1
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G_BR %bb.2
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bb.1:
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%5:sgpr(s64) = COPY %1
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G_BR %bb.2
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bb.2:
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%6:sgpr(s64) = G_PHI %0(s64), %bb.0, %5(s64), %bb.1
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$sgpr0_sgpr1 = COPY %6
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: g_phi_v2s16_vv_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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; GCN-LABEL: name: g_phi_v2s16_vv_sbranch
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: liveins: $vgpr0, $vgpr1, $sgpr2
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: $scc = COPY [[COPY3]]
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; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
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; GCN: S_BRANCH %bb.2
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY1]]
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; GCN: S_BRANCH %bb.2
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; GCN: bb.2:
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; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
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; GCN: $vgpr0 = COPY [[PHI]]
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; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr2
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = COPY $vgpr1
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %4(s1), %bb.1
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G_BR %bb.2
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bb.1:
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%5:sgpr(<2 x s16>) = COPY %1
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G_BR %bb.2
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bb.2:
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%6:vgpr(<2 x s16>) = G_PHI %0(<2 x s16>), %bb.0, %5(<2 x s16>), %bb.1
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$vgpr0 = COPY %6
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: g_phi_vcc_s1_sbranch
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr2
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_CONSTANT i32 0
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%4:vcc(s1) = G_ICMP intpred(eq), %0, %3
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%5:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
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G_BRCOND %5(s1), %bb.1
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G_BR %bb.2
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bb.1:
|
||||
%6:vcc(s1) = G_ICMP intpred(eq), %1, %3
|
||||
G_BR %bb.2
|
||||
|
||||
bb.2:
|
||||
%7:vcc(s1) = G_PHI %4, %bb.0, %6, %bb.1
|
||||
S_SETPC_B64 undef $sgpr30_sgpr31, implicit %7
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: phi_s32_ss_sbranch
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; GCN-LABEL: name: phi_s32_ss_sbranch
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY3]]
|
||||
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GCN: S_BRANCH %bb.2
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: S_BRANCH %bb.2
|
||||
; GCN: bb.2:
|
||||
; GCN: [[PHI:%[0-9]+]]:sreg_32_xm0 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
|
||||
; GCN: $sgpr0 = COPY [[PHI]]
|
||||
; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1, $sgpr2
|
||||
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
%5:sgpr(s32) = COPY %1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.2:
|
||||
%6:sgpr(s32) = PHI %0(s32), %bb.0, %5(s32), %bb.1
|
||||
$sgpr0 = COPY %6(s32)
|
||||
S_SETPC_B64 undef $sgpr30_sgpr31
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: phi_s32_vv_sbranch
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; GCN-LABEL: name: phi_s32_vv_sbranch
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: liveins: $vgpr0, $vgpr1, $sgpr2
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GCN: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
|
||||
; GCN: $scc = COPY [[COPY3]]
|
||||
; GCN: S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
; GCN: S_BRANCH %bb.2
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY1]]
|
||||
; GCN: S_BRANCH %bb.2
|
||||
; GCN: bb.2:
|
||||
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY4]], %bb.1
|
||||
; GCN: $vgpr0 = COPY [[PHI]]
|
||||
; GCN: S_SETPC_B64 undef $sgpr30_sgpr31
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1, $sgpr2
|
||||
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:sgpr(s32) = COPY $sgpr2
|
||||
%3:sgpr(s32) = G_CONSTANT i32 0
|
||||
%4:scc(s1) = G_ICMP intpred(eq), %2(s32), %3
|
||||
G_BRCOND %4(s1), %bb.1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.1:
|
||||
%5:sgpr(s32) = COPY %1
|
||||
G_BR %bb.2
|
||||
|
||||
bb.2:
|
||||
%6:vgpr(s32) = PHI %0(s32), %bb.0, %5(s32), %bb.1
|
||||
$vgpr0 = COPY %6
|
||||
S_SETPC_B64 undef $sgpr30_sgpr31
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user