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Implement computeKnownBits for scalar_to_vector
Differential Revision: https://reviews.llvm.org/D54728 llvm-svn: 347274
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@ -2345,6 +2345,19 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
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}
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break;
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}
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case ISD::SCALAR_TO_VECTOR: {
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// We know about scalar_to_vector as much as we know about it source,
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// which becomes the first element of otherwise unknown vector.
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if (DemandedElts != 1)
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break;
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SDValue N0 = Op.getOperand(0);
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Known = computeKnownBits(N0, DemandedElts, Depth + 1);
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if (N0.getValueSizeInBits() != BitWidth)
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Known = Known.trunc(BitWidth);
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break;
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}
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case ISD::BITCAST: {
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SDValue N0 = Op.getOperand(0);
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EVT SubVT = N0.getValueType();
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@ -305,8 +305,11 @@ entry:
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; GFX9-NEXT: s_waitcnt
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; GFX9-NEXT: s_setpc_b64
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; VI: flat_load_ubyte v{{[0-9]+}}
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; VI: v_or_b32_e32
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; VI: flat_load_ubyte [[LO:v[0-9]+]]
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; VI: v_lshrrev_b32_e32 [[HI:v[0-9]+]], 16, v2
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; VI: s_mov_b32 [[MASK:s[0-9]+]], 0x5040c00
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; VI: v_perm_b32 [[RES:v[0-9]+]], [[HI]], [[LO]], [[MASK]]
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; VI: flat_store_dword v[0:1], [[RES]]
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define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {
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entry:
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%reg.bc = bitcast i32 %reg to <2 x i16>
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