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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 03:33:20 +01:00
Make DenseMap's insert return a pair, to more closely resemble std::map.
llvm-svn: 53177
This commit is contained in:
parent
1d321b8875
commit
c97817aac3
@ -147,14 +147,16 @@ public:
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return end();
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}
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bool insert(const std::pair<KeyT, ValueT> &KV) {
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std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
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BucketT *TheBucket;
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if (LookupBucketFor(KV.first, TheBucket))
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return false; // Already in map.
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return std::make_pair(iterator(TheBucket, Buckets+NumBuckets),
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false); // Already in map.
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// Otherwise, insert the new element.
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InsertIntoBucket(KV.first, KV.second, TheBucket);
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return true;
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TheBucket = InsertIntoBucket(KV.first, KV.second, TheBucket);
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return std::make_pair(iterator(TheBucket, Buckets+NumBuckets),
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true);
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}
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bool erase(const KeyT &Val) {
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@ -41,10 +41,6 @@ public:
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return TheMap.count(V);
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}
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bool insert(const ValueT &V) {
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return TheMap.insert(std::make_pair(V, 0));
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}
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void erase(const ValueT &V) {
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TheMap.erase(V);
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}
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@ -90,6 +86,10 @@ public:
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const_iterator begin() const { return ConstIterator(TheMap.begin()); }
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const_iterator end() const { return ConstIterator(TheMap.end()); }
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std::pair<iterator, bool> insert(const ValueT &V) {
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return TheMap.insert(std::make_pair(V, 0));
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}
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};
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} // end namespace llvm
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@ -115,7 +115,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize {
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LegalizedNodes.insert(std::make_pair(To, To));
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}
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void AddPromotedOperand(SDOperand From, SDOperand To) {
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bool isNew = PromotedNodes.insert(std::make_pair(From, To));
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bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
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assert(isNew && "Got into the map somehow?");
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// If someone requests legalization of the new node, return itself.
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LegalizedNodes.insert(std::make_pair(To, To));
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@ -6734,7 +6734,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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}
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// Remember in a map if the values will be reused later.
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bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
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bool isNew =
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ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
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assert(isNew && "Value already expanded?!?");
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}
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@ -413,9 +413,10 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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unsigned VRBase = 0;
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Just use the input register directly!
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SDOperand Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(SDOperand(Node, ResNo));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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return;
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@ -472,9 +473,10 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
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}
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SDOperand Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(SDOperand(Node, ResNo));
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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@ -532,7 +534,8 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
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SDOperand Op(Node, i);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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@ -786,7 +789,8 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
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} else
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assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
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bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
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SDOperand Op(Node, 0);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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@ -992,7 +996,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
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// Copy from physical register.
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assert(I->Reg && "Unknown physical register!");
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unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
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bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
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bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
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@ -114,7 +114,7 @@ public:
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/// insert - This returns true if the pointer was new to the set, false if it
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/// was already in the set.
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bool insert(const Type *Src, const Type *Dst) {
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if (!TheMap.insert(std::make_pair(Src, PATypeHolder(Dst))))
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if (!TheMap.insert(std::make_pair(Src, PATypeHolder(Dst))).second)
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return false; // Already in map.
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if (Src->isAbstract())
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Src->addAbstractTypeUser(this);
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@ -209,11 +209,13 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
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unsigned RegOp = OpTbl2Addr[i][0];
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unsigned MemOp = OpTbl2Addr[i][1];
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if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
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if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
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MemOp)).second)
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assert(false && "Duplicated entries?");
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unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
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if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
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std::make_pair(RegOp, AuxInfo))))
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std::make_pair(RegOp,
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AuxInfo))).second)
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AmbEntries.push_back(MemOp);
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}
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@ -297,14 +299,15 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
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unsigned RegOp = OpTbl0[i][0];
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unsigned MemOp = OpTbl0[i][1];
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if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
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if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
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MemOp)).second)
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assert(false && "Duplicated entries?");
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unsigned FoldedLoad = OpTbl0[i][2];
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// Index 0, folded load or store.
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unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
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if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
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if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
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std::make_pair(RegOp, AuxInfo))))
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std::make_pair(RegOp, AuxInfo))).second)
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AmbEntries.push_back(MemOp);
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}
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@ -423,12 +426,13 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
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unsigned RegOp = OpTbl1[i][0];
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unsigned MemOp = OpTbl1[i][1];
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if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
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if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
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MemOp)).second)
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assert(false && "Duplicated entries?");
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unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
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if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
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if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
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std::make_pair(RegOp, AuxInfo))))
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std::make_pair(RegOp, AuxInfo))).second)
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AmbEntries.push_back(MemOp);
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}
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@ -629,11 +633,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
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unsigned RegOp = OpTbl2[i][0];
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unsigned MemOp = OpTbl2[i][1];
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if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
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if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
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MemOp)).second)
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assert(false && "Duplicated entries?");
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unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
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if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
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std::make_pair(RegOp, AuxInfo))))
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std::make_pair(RegOp, AuxInfo))).second)
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AmbEntries.push_back(MemOp);
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}
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@ -85,7 +85,7 @@ namespace {
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/// AddToWorkList - Add the specified instruction to the worklist if it
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/// isn't already in it.
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void AddToWorkList(Instruction *I) {
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if (WorklistMap.insert(std::make_pair(I, Worklist.size())))
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if (WorklistMap.insert(std::make_pair(I, Worklist.size())).second)
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Worklist.push_back(I);
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}
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