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AMDGPU/GlobalISel: Enable s_{and|or}n2_{b32|b64} patterns
This commit is contained in:
Matt Arsenault
parent
7abe7a3b10
commit
c97959510d
@ -408,8 +408,14 @@ class SOP2_64_32_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
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class UniformUnaryFrag<SDPatternOperator Op> : PatFrag <
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(ops node:$src0),
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(Op $src0),
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[{ return !N->isDivergent(); }]
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>;
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[{ return !N->isDivergent(); }]> {
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// This check is unnecessary as it's captured by the result register
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// bank constraint.
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//
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// FIXME: Should add a way for the emitter to recognize this is a
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// trivially true predicate to eliminate the check.
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let GISelPredicateCode = [{return true;}];
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}
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class UniformBinFrag<SDPatternOperator Op> : PatFrag <
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(ops node:$src0, node:$src1),
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@ -5,8 +5,7 @@
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define amdgpu_ps i32 @s_andn2_i32(i32 inreg %src0, i32 inreg %src1) {
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; GCN-LABEL: s_andn2_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s0, s3
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; GCN-NEXT: s_and_b32 s0, s2, s0
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; GCN-NEXT: s_andn2_b32 s0, s2, s3
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i32 %src1, -1
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%and = and i32 %src0, %not.src1
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@ -16,8 +15,7 @@ define amdgpu_ps i32 @s_andn2_i32(i32 inreg %src0, i32 inreg %src1) {
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define amdgpu_ps i32 @s_andn2_i32_commute(i32 inreg %src0, i32 inreg %src1) {
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; GCN-LABEL: s_andn2_i32_commute:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s0, s3
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; GCN-NEXT: s_and_b32 s0, s0, s2
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; GCN-NEXT: s_andn2_b32 s0, s2, s3
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i32 %src1, -1
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%and = and i32 %not.src1, %src0
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@ -28,7 +26,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_use(i32 inreg %src0, i32 inreg
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; GCN-LABEL: s_andn2_i32_multi_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s1, s3
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; GCN-NEXT: s_and_b32 s0, s2, s1
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; GCN-NEXT: s_andn2_b32 s0, s2, s3
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i32 %src1, -1
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%and = and i32 %src0, %not.src1
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@ -40,9 +38,8 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_use(i32 inreg %src0, i32 inreg
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define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_foldable_use(i32 inreg %src0, i32 inreg %src1, i32 inreg %src2) {
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; GCN-LABEL: s_andn2_i32_multi_foldable_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s1, s4
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; GCN-NEXT: s_and_b32 s0, s2, s1
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; GCN-NEXT: s_and_b32 s1, s3, s1
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; GCN-NEXT: s_andn2_b32 s0, s2, s4
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; GCN-NEXT: s_andn2_b32 s1, s3, s4
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; GCN-NEXT: ; return to shader part epilog
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%not.src2 = xor i32 %src2, -1
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%and0 = and i32 %src0, %not.src2
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@ -91,8 +88,7 @@ define amdgpu_ps float @v_andn2_i32_vs(i32 %src0, i32 inreg %src1) {
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define amdgpu_ps i64 @s_andn2_i64(i64 inreg %src0, i64 inreg %src1) {
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; GCN-LABEL: s_andn2_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[0:1], s[4:5]
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; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i64 %src1, -1
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%and = and i64 %src0, %not.src1
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@ -102,8 +98,7 @@ define amdgpu_ps i64 @s_andn2_i64(i64 inreg %src0, i64 inreg %src1) {
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define amdgpu_ps i64 @s_andn2_i64_commute(i64 inreg %src0, i64 inreg %src1) {
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; GCN-LABEL: s_andn2_i64_commute:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[0:1], s[4:5]
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; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
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; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i64 %src1, -1
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%and = and i64 %not.src1, %src0
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@ -113,9 +108,8 @@ define amdgpu_ps i64 @s_andn2_i64_commute(i64 inreg %src0, i64 inreg %src1) {
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define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_foldable_use(i64 inreg %src0, i64 inreg %src1, i64 inreg %src2) {
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; GCN-LABEL: s_andn2_i64_multi_foldable_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[6:7], s[6:7]
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; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7]
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; GCN-NEXT: s_and_b64 s[2:3], s[4:5], s[6:7]
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; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[6:7]
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; GCN-NEXT: s_andn2_b64 s[2:3], s[4:5], s[6:7]
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; GCN-NEXT: ; return to shader part epilog
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%not.src2 = xor i64 %src2, -1
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%and0 = and i64 %src0, %not.src2
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@ -128,10 +122,10 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_foldable_use(i64 inreg %src0, i
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define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_use(i64 inreg %src0, i64 inreg %src1) {
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; GCN-LABEL: s_andn2_i64_multi_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[4:5], s[4:5]
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; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: s_mov_b32 s2, s4
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; GCN-NEXT: s_mov_b32 s3, s5
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; GCN-NEXT: s_not_b64 s[6:7], s[4:5]
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; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: s_mov_b32 s2, s6
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; GCN-NEXT: s_mov_b32 s3, s7
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i64 %src1, -1
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%and = and i64 %src0, %not.src1
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@ -5,8 +5,7 @@
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define amdgpu_ps i32 @s_orn2_i32(i32 inreg %src0, i32 inreg %src1) {
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; GCN-LABEL: s_orn2_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s0, s3
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; GCN-NEXT: s_or_b32 s0, s2, s0
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; GCN-NEXT: s_orn2_b32 s0, s2, s3
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i32 %src1, -1
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%or = or i32 %src0, %not.src1
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@ -16,8 +15,7 @@ define amdgpu_ps i32 @s_orn2_i32(i32 inreg %src0, i32 inreg %src1) {
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define amdgpu_ps i32 @s_orn2_i32_commute(i32 inreg %src0, i32 inreg %src1) {
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; GCN-LABEL: s_orn2_i32_commute:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s0, s3
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; GCN-NEXT: s_or_b32 s0, s0, s2
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; GCN-NEXT: s_orn2_b32 s0, s2, s3
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i32 %src1, -1
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%or = or i32 %not.src1, %src0
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@ -28,7 +26,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_use(i32 inreg %src0, i32 inreg %
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; GCN-LABEL: s_orn2_i32_multi_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s1, s3
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; GCN-NEXT: s_or_b32 s0, s2, s1
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; GCN-NEXT: s_orn2_b32 s0, s2, s3
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i32 %src1, -1
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%or = or i32 %src0, %not.src1
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@ -40,9 +38,8 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_use(i32 inreg %src0, i32 inreg %
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define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_foldable_use(i32 inreg %src0, i32 inreg %src1, i32 inreg %src2) {
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; GCN-LABEL: s_orn2_i32_multi_foldable_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b32 s1, s4
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; GCN-NEXT: s_or_b32 s0, s2, s1
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; GCN-NEXT: s_or_b32 s1, s3, s1
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; GCN-NEXT: s_orn2_b32 s0, s2, s4
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; GCN-NEXT: s_orn2_b32 s1, s3, s4
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; GCN-NEXT: ; return to shader part epilog
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%not.src2 = xor i32 %src2, -1
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%or0 = or i32 %src0, %not.src2
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@ -91,8 +88,7 @@ define amdgpu_ps float @v_orn2_i32_vs(i32 %src0, i32 inreg %src1) {
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define amdgpu_ps i64 @s_orn2_i64(i64 inreg %src0, i64 inreg %src1) {
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; GCN-LABEL: s_orn2_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[0:1], s[4:5]
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i64 %src1, -1
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%or = or i64 %src0, %not.src1
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@ -102,8 +98,7 @@ define amdgpu_ps i64 @s_orn2_i64(i64 inreg %src0, i64 inreg %src1) {
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define amdgpu_ps i64 @s_orn2_i64_commute(i64 inreg %src0, i64 inreg %src1) {
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; GCN-LABEL: s_orn2_i64_commute:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[0:1], s[4:5]
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; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
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; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i64 %src1, -1
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%or = or i64 %not.src1, %src0
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@ -113,9 +108,8 @@ define amdgpu_ps i64 @s_orn2_i64_commute(i64 inreg %src0, i64 inreg %src1) {
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define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_foldable_use(i64 inreg %src0, i64 inreg %src1, i64 inreg %src2) {
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; GCN-LABEL: s_orn2_i64_multi_foldable_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[6:7], s[6:7]
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7]
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; GCN-NEXT: s_or_b64 s[2:3], s[4:5], s[6:7]
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; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[6:7]
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; GCN-NEXT: s_orn2_b64 s[2:3], s[4:5], s[6:7]
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; GCN-NEXT: ; return to shader part epilog
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%not.src2 = xor i64 %src2, -1
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%or0 = or i64 %src0, %not.src2
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@ -128,10 +122,10 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_foldable_use(i64 inreg %src0, i6
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define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_use(i64 inreg %src0, i64 inreg %src1) {
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; GCN-LABEL: s_orn2_i64_multi_use:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_not_b64 s[4:5], s[4:5]
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: s_mov_b32 s2, s4
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; GCN-NEXT: s_mov_b32 s3, s5
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; GCN-NEXT: s_not_b64 s[6:7], s[4:5]
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; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]
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; GCN-NEXT: s_mov_b32 s2, s6
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; GCN-NEXT: s_mov_b32 s3, s7
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; GCN-NEXT: ; return to shader part epilog
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%not.src1 = xor i64 %src1, -1
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%or = or i64 %src0, %not.src1
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