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R600: Use optimized 24bit path in udivrem
v2: drop enum keyword
use correct extension mode
don't bother computing the sign in unsinged case
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 215462
This commit is contained in:
Jan Vesely
parent
a72063b855
commit
c9798145af
@ -1387,7 +1387,7 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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// This is a shortcut for integer division because we have fast i32<->f32
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// conversions, and fast f32 reciprocal instructions. The fractional part of a
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// float is enough to accurately represent up to a 24-bit integer.
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SDValue AMDGPUTargetLowering::LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) const {
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SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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@ -1395,6 +1395,9 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) cons
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MVT IntVT = MVT::i32;
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MVT FltVT = MVT::f32;
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ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
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ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
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if (VT.isVector()) {
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unsigned NElts = VT.getVectorNumElements();
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IntVT = MVT::getVectorVT(MVT::i32, NElts);
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@ -1403,8 +1406,11 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) cons
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unsigned BitSize = VT.getScalarType().getSizeInBits();
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SDValue jq = DAG.getConstant(1, IntVT);
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if (sign) {
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// char|short jq = ia ^ ib;
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SDValue jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
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jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
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// jq = jq >> (bitsize - 2)
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jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
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@ -1414,18 +1420,21 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) cons
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// jq = (int)jq
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jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
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}
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// int ia = (int)LHS;
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SDValue ia = DAG.getSExtOrTrunc(LHS, DL, IntVT);
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SDValue ia = sign ?
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DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
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// int ib, (int)RHS;
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SDValue ib = DAG.getSExtOrTrunc(RHS, DL, IntVT);
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SDValue ib = sign ?
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DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
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// float fa = (float)ia;
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SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FltVT, ia);
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SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
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// float fb = (float)ib;
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SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FltVT, ib);
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SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
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// float fq = native_divide(fa, fb);
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SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
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@ -1442,7 +1451,7 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) cons
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DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
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// int iq = (int)fq;
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SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, IntVT, fq);
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SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
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// fr = fabs(fr);
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fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
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@ -1458,11 +1467,13 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) cons
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// jq = (cv ? jq : 0);
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jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
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// dst = iq + jq;
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iq = DAG.getSExtOrTrunc(iq, DL, VT);
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// dst = trunc/extend to legal type
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iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
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// dst = iq + jq;
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SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
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// Rem needs compensation, it's easier to recompute it
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SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
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Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
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@ -1481,6 +1492,16 @@ SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
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SDValue Num = Op.getOperand(0);
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SDValue Den = Op.getOperand(1);
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if (VT == MVT::i32) {
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if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
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DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
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// TODO: We technically could do this for i64, but shouldn't that just be
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// handled by something generally reducing 64-bit division on 32-bit
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// values to 32-bit?
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return LowerDIVREM24(Op, DAG, false);
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}
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}
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// RCP = URECIP(Den) = 2^32 / Den + e
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// e is rounding error.
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SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
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@ -1591,7 +1612,7 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
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// TODO: We technically could do this for i64, but shouldn't that just be
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// handled by something generally reducing 64-bit division on 32-bit
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// values to 32-bit?
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return LowerSDIVREM24(Op, DAG);
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return LowerDIVREM24(Op, DAG, true);
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}
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}
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@ -82,7 +82,7 @@ protected:
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
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bool isHWTrueValue(SDValue Op) const;
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bool isHWFalseValue(SDValue Op) const;
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244
test/CodeGen/R600/udivrem24.ll
Normal file
244
test/CodeGen/R600/udivrem24.ll
Normal file
@ -0,0 +1,244 @@
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: @udiv24_i8
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; SI: V_CVT_F32_UBYTE
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; SI: V_CVT_F32_UBYTE
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; SI: V_RCP_F32
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; SI: V_CVT_U32_F32
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; EG: UINT_TO_FLT
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; EG-DAG: UINT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_UINT
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define void @udiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
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%num = load i8 addrspace(1) * %in
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%den = load i8 addrspace(1) * %den_ptr
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%result = udiv i8 %num, %den
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store i8 %result, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @udiv24_i16
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; SI: V_CVT_F32_U32
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; SI: V_CVT_F32_U32
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; SI: V_RCP_F32
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; SI: V_CVT_U32_F32
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; EG: UINT_TO_FLT
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; EG-DAG: UINT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_UINT
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define void @udiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
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%num = load i16 addrspace(1) * %in, align 2
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%den = load i16 addrspace(1) * %den_ptr, align 2
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%result = udiv i16 %num, %den
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store i16 %result, i16 addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: @udiv24_i32
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; SI: V_CVT_F32_U32
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; SI-DAG: V_CVT_F32_U32
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; SI-DAG: V_RCP_F32
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; SI: V_CVT_U32_F32
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; EG: UINT_TO_FLT
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; EG-DAG: UINT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_UINT
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define void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = lshr i32 %num.i24.0, 8
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%den.i24 = lshr i32 %den.i24.0, 8
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%result = udiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @udiv25_i32
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; RCP_IFLAG is for URECIP in the full 32b alg
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; SI: V_RCP_IFLAG
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; SI-NOT: V_RCP_F32
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; EG-NOT: UINT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @udiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = lshr i32 %num.i24.0, 7
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%den.i24 = lshr i32 %den.i24.0, 7
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%result = udiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_udiv24_i32_1
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; RCP_IFLAG is for URECIP in the full 32b alg
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; SI: V_RCP_IFLAG
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; SI-NOT: V_RCP_F32
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; EG-NOT: UINT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_udiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = lshr i32 %num.i24.0, 8
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%den.i24 = lshr i32 %den.i24.0, 7
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%result = udiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_udiv24_i32_2
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; RCP_IFLAG is for URECIP in the full 32b alg
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; SI: V_RCP_IFLAG
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; SI-NOT: V_RCP_F32
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; EG-NOT: UINT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_udiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = lshr i32 %num.i24.0, 7
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%den.i24 = lshr i32 %den.i24.0, 8
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%result = udiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @urem24_i8
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; SI: V_CVT_F32_UBYTE
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; SI: V_CVT_F32_UBYTE
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; SI: V_RCP_F32
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; SI: V_CVT_U32_F32
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; EG: UINT_TO_FLT
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; EG-DAG: UINT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_UINT
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define void @urem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
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%num = load i8 addrspace(1) * %in
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%den = load i8 addrspace(1) * %den_ptr
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%result = urem i8 %num, %den
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store i8 %result, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @urem24_i16
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; SI: V_CVT_F32_U32
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; SI: V_CVT_F32_U32
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; SI: V_RCP_F32
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; SI: V_CVT_U32_F32
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; EG: UINT_TO_FLT
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; EG-DAG: UINT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_UINT
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define void @urem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
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%num = load i16 addrspace(1) * %in, align 2
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%den = load i16 addrspace(1) * %den_ptr, align 2
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%result = urem i16 %num, %den
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store i16 %result, i16 addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: @urem24_i32
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; SI: V_CVT_F32_U32
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; SI: V_CVT_F32_U32
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; SI: V_RCP_F32
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; SI: V_CVT_U32_F32
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; EG: UINT_TO_FLT
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; EG-DAG: UINT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_UINT
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define void @urem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = lshr i32 %num.i24.0, 8
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%den.i24 = lshr i32 %den.i24.0, 8
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%result = urem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @urem25_i32
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; RCP_IFLAG is for URECIP in the full 32b alg
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; SI: V_RCP_IFLAG
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; SI-NOT: V_RCP_F32
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; EG-NOT: UINT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @urem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = lshr i32 %num.i24.0, 7
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%den.i24 = lshr i32 %den.i24.0, 7
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%result = urem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_urem24_i32_1
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; RCP_IFLAG is for URECIP in the full 32b alg
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; SI: V_RCP_IFLAG
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; SI-NOT: V_RCP_F32
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; EG-NOT: UINT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_urem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = lshr i32 %num.i24.0, 8
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%den.i24 = lshr i32 %den.i24.0, 7
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%result = urem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_urem24_i32_2
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; RCP_IFLAG is for URECIP in the full 32b alg
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; SI: V_RCP_IFLAG
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; SI-NOT: V_RCP_F32
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; EG-NOT: UINT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_urem24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
|
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%den = load i32 addrspace(1) * %den_ptr, align 4
|
||||
%num.i24.0 = shl i32 %num, 7
|
||||
%den.i24.0 = shl i32 %den, 8
|
||||
%num.i24 = lshr i32 %num.i24.0, 7
|
||||
%den.i24 = lshr i32 %den.i24.0, 8
|
||||
%result = urem i32 %num.i24, %den.i24
|
||||
store i32 %result, i32 addrspace(1)* %out, align 4
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user