From c9838f5f9f6ec1eb7e8475c94e2613a8c3300785 Mon Sep 17 00:00:00 2001 From: Yvan Roux Date: Wed, 25 Mar 2020 16:40:30 +0100 Subject: [PATCH] [ARM] Move ConstantIsland and LowOverheadLoops Passes. Move ARM ConstantIsland and LowOverheadLopps passes later in the pipeline such that they will be run after the upcoming Machine Outlining pass. Differential Revision: https://reviews.llvm.org/D76065 --- lib/Target/ARM/ARMTargetMachine.cpp | 3 +++ test/CodeGen/ARM/O3-pipeline.ll | 6 +++--- test/DebugInfo/ARM/cfi-eof-prologue.mir | 6 ++++++ test/DebugInfo/MIR/ARM/larger-subregister.mir | 3 +++ test/DebugInfo/MIR/ARM/param-reg-const-mix.mir | 4 +++- test/DebugInfo/MIR/ARM/subregister-full-piece.mir | 4 ++++ 6 files changed, 22 insertions(+), 4 deletions(-) diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 63aa65267ef..947bbc3ad3e 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -362,6 +362,7 @@ public: void addPreRegAlloc() override; void addPreSched2() override; void addPreEmitPass() override; + void addPreEmitPass2() override; std::unique_ptr getCSEConfig() const override; }; @@ -541,7 +542,9 @@ void ARMPassConfig::addPreEmitPass() { // Don't optimize barriers at -O0. if (getOptLevel() != CodeGenOpt::None) addPass(createARMOptimizeBarriersPass()); +} +void ARMPassConfig::addPreEmitPass2() { addPass(createARMConstantIslandPass()); addPass(createARMLowOverheadLoopsPass()); diff --git a/test/CodeGen/ARM/O3-pipeline.ll b/test/CodeGen/ARM/O3-pipeline.ll index 44fcf2a756b..6c1a1b22f7f 100644 --- a/test/CodeGen/ARM/O3-pipeline.ll +++ b/test/CodeGen/ARM/O3-pipeline.ll @@ -161,15 +161,15 @@ ; CHECK-NEXT: Thumb2 instruction size reduce pass ; CHECK-NEXT: Unpack machine instruction bundles ; CHECK-NEXT: optimise barriers pass +; CHECK-NEXT: Contiguously Lay Out Funclets +; CHECK-NEXT: StackMap Liveness Analysis +; CHECK-NEXT: Live DEBUG_VALUE analysis ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: ARM constant island placement and branch shortening pass ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Machine Natural Loop Construction ; CHECK-NEXT: ReachingDefAnalysis ; CHECK-NEXT: ARM Low Overhead Loops pass -; CHECK-NEXT: Contiguously Lay Out Funclets -; CHECK-NEXT: StackMap Liveness Analysis -; CHECK-NEXT: Live DEBUG_VALUE analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: ARM Assembly Printer diff --git a/test/DebugInfo/ARM/cfi-eof-prologue.mir b/test/DebugInfo/ARM/cfi-eof-prologue.mir index ab8154edf8c..ea68187e32a 100644 --- a/test/DebugInfo/ARM/cfi-eof-prologue.mir +++ b/test/DebugInfo/ARM/cfi-eof-prologue.mir @@ -139,6 +139,7 @@ --- name: _ZN1BC2Ev alignment: 2 +tracksRegLiveness: true liveins: - { reg: '$r0' } frameInfo: @@ -154,6 +155,8 @@ stack: callee-saved-register: '$r4' } body: | bb.0.entry: + liveins: $r0, $r4, $lr + frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -175,6 +178,7 @@ body: | --- name: _ZN1BC1Ev alignment: 2 +tracksRegLiveness: true liveins: - { reg: '$r0' } frameInfo: @@ -190,6 +194,8 @@ stack: callee-saved-register: '$r4' } body: | bb.0.entry: + liveins: $r0, $r4, $lr + frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 diff --git a/test/DebugInfo/MIR/ARM/larger-subregister.mir b/test/DebugInfo/MIR/ARM/larger-subregister.mir index 6fb944e8c97..a9d1dd44192 100644 --- a/test/DebugInfo/MIR/ARM/larger-subregister.mir +++ b/test/DebugInfo/MIR/ARM/larger-subregister.mir @@ -29,8 +29,11 @@ !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14) !14 = !DICompositeType(tag: DW_TAG_structure_type, name: "CGRect", scope: !5, file: !3, line: 46, size: 128, elements: !4, runtimeLang: DW_LANG_Swift, identifier: "$sSo6CGRectVD") name: 'f' +tracksRegLiveness: true body: | bb.0: + liveins: $r6 + DBG_VALUE $s31, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !10 DBG_VALUE $q8, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !10 renamable $r0 = t2ADDri $r6, 144, 14, $noreg, $noreg, debug-location !10 diff --git a/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir b/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir index 99511280f22..83b5a6f394d 100644 --- a/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir +++ b/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir @@ -67,9 +67,11 @@ ... --- name: fn1 -tracksRegLiveness: false +tracksRegLiveness: true body: | bb.0.entry: + liveins: $r0, $r1, $r4, $lr + $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr $r4 = MOVr $r0, 14, $noreg, $noreg DBG_VALUE $r1, $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !18 diff --git a/test/DebugInfo/MIR/ARM/subregister-full-piece.mir b/test/DebugInfo/MIR/ARM/subregister-full-piece.mir index fe1660d7f23..1fa172b9764 100644 --- a/test/DebugInfo/MIR/ARM/subregister-full-piece.mir +++ b/test/DebugInfo/MIR/ARM/subregister-full-piece.mir @@ -39,8 +39,12 @@ !9 = !DILocalVariable(name: "q9", scope: !5, file: !4, line: 1, type: !7) !20 = !DILocation(line: 0, scope: !5) name: f +tracksRegLiveness: true body: | bb.2.for.body: + liveins: $r2 + + t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr t2Bcc %bb.2.for.body, 0, killed $cpsr, debug-location !20 DBG_VALUE $q8, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 0, 64), debug-location !20 DBG_VALUE $q9, $noreg, !9, !DIExpression(DW_OP_LLVM_fragment, 0, 56), debug-location !20