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[Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.
llvm-svn: 224991
This commit is contained in:
Colin LeMahieu
parent
300c89d245
commit
c9924ffc90
@ -128,63 +128,129 @@ def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
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def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
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def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
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}
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}
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// Generate frame index addresses.
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// Pats for instruction selection.
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let hasSideEffects = 0, isReMaterializable = 1,
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isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
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def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
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(ins IntRegs:$src1, s32Imm:$offset),
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"$dst = add($src1, ##$offset)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=cmp.eq(Rs,#s8)
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// A class to embed the usual comparison patfrags within a zext to i32.
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let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
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// The seteq/setne frags use "lhs" and "rhs" as operands, so use the same
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isExtentSigned = 1, opExtentBits = 8 in
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// names, or else the frag's "body" won't match the operands.
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def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
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class CmpInReg<PatFrag Op>
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(ins IntRegs:$Rs, s8Ext:$s8),
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: PatFrag<(ops node:$lhs, node:$rhs),(i32 (zext (i1 Op.Fragment)))>;
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"$Rd = cmp.eq($Rs, #$s8)",
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[(set (i32 IntRegs:$Rd),
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(i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
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s8ExtPred:$s8)))))]>,
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Requires<[HasV4T]>;
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// Preserve the TSTBIT generation
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def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
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def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
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class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
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: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
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"$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
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ImmRegRel {
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let validSubTargets = HasV4SubT;
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let InputType = "reg";
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let CextOpcode = mnemonic;
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let isCompare = 1;
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let isCommutable = IsComm;
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let hasSideEffects = 0;
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bits<2> Pd;
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bits<5> Rs;
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bits<5> Rt;
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let IClass = 0b1100;
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let Inst{27-21} = 0b0111110;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{7-5} = MinOp;
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let Inst{1-0} = Pd;
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}
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let isCodeGenOnly = 0 in {
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def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
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def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
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def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
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def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
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def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
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def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
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}
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class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
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Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
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: ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
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"$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
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ImmRegRel {
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let validSubTargets = HasV4SubT;
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let InputType = "imm";
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let CextOpcode = mnemonic;
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let isCompare = 1;
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let isCommutable = IsComm;
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let hasSideEffects = 0;
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let isExtendable = IsImmExt;
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let opExtendable = !if (IsImmExt, 2, 0);
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let isExtentSigned = IsImmSigned;
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let opExtentBits = ImmBits;
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bits<2> Pd;
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bits<5> Rs;
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bits<8> Imm;
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let IClass = 0b1101;
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let Inst{27-24} = 0b1101;
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let Inst{22-21} = MajOp;
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let Inst{20-16} = Rs;
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let Inst{12-5} = Imm;
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let Inst{4} = 0b0;
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let Inst{3} = IsHalf;
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let Inst{1-0} = Pd;
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}
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let isCodeGenOnly = 0 in {
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def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
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def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
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def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
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def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
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def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
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def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
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}
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class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
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: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
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"$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
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ImmRegRel {
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let validSubTargets = HasV4SubT;
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let InputType = "imm";
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let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
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let isExtendable = 1;
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let opExtendable = 2;
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let isExtentSigned = 1;
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let opExtentBits = 8;
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let hasNewValue = 1;
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bits<5> Rd;
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bits<5> Rs;
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bits<8> s8;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0011;
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let Inst{22} = 0b1;
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let Inst{21} = IsNeg;
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let Inst{20-16} = Rs;
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let Inst{13} = 0b1;
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let Inst{12-5} = s8;
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let Inst{4-0} = Rd;
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}
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let isCodeGenOnly = 0 in {
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def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
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def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
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}
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def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
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(A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
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def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
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(A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
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// Preserve the S2_tstbit_r generation
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def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
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def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
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(i32 IntRegs:$src1))), 0)))),
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(i32 IntRegs:$src1))), 0)))),
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(i32 (C2_muxii (i1 (S2_tstbit_r (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
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1, 0))>;
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// Interfered with tstbit generation, above pattern preserves, see : tstbit.ll
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// Rd=cmp.ne(Rs,#s8)
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let validSubTargets = HasV4SubT, isExtendable = 1, opExtendable = 2,
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isExtentSigned = 1, opExtentBits = 8 in
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def V4_A4_rcmpneqi : ALU32_ri<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, s8Ext:$s8),
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"$Rd = !cmp.eq($Rs, #$s8)",
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[(set (i32 IntRegs:$Rd),
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(i32 (zext (i1 (setne (i32 IntRegs:$Rs),
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s8ExtPred:$s8)))))]>,
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Requires<[HasV4T]>;
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// Rd=cmp.eq(Rs,Rt)
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let validSubTargets = HasV4SubT in
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def V4_A4_rcmpeq : ALU32_ri<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd = cmp.eq($Rs, $Rt)",
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[(set (i32 IntRegs:$Rd),
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(i32 (zext (i1 (seteq (i32 IntRegs:$Rs),
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IntRegs:$Rt)))))]>,
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Requires<[HasV4T]>;
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// Rd=cmp.ne(Rs,Rt)
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let validSubTargets = HasV4SubT in
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def V4_A4_rcmpneq : ALU32_ri<(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, IntRegs:$Rt),
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"$Rd = !cmp.eq($Rs, $Rt)",
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[(set (i32 IntRegs:$Rd),
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(i32 (zext (i1 (setne (i32 IntRegs:$Rs),
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IntRegs:$Rt)))))]>,
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Requires<[HasV4T]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU32 -
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// ALU32 -
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@ -60,6 +60,10 @@
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# CHECK: p3 = cmp.gtu(r21, r31)
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# CHECK: p3 = cmp.gtu(r21, r31)
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0x13 0xdf 0x75 0xf2
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0x13 0xdf 0x75 0xf2
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# CHECK: p3 = !cmp.gtu(r21, r31)
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# CHECK: p3 = !cmp.gtu(r21, r31)
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0xf1 0xe3 0x55 0x73
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# CHECK: r17 = cmp.eq(r21, #31)
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0xf1 0xe3 0x75 0x73
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# CHECK: r17 = !cmp.eq(r21, #31)
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0x11 0xdf 0x55 0xf3
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0x11 0xdf 0x55 0xf3
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# CHECK: r17 = cmp.eq(r21, r31)
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# CHECK: r17 = cmp.eq(r21, r31)
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0x11 0xdf 0x75 0xf3
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0x11 0xdf 0x75 0xf3
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@ -1,5 +1,29 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x43 0xd5 0xd1 0xc7
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# CHECK: p3 = cmpb.gt(r17, r21)
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0xc3 0xd5 0xd1 0xc7
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# CHECK: p3 = cmpb.eq(r17, r21)
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0xe3 0xd5 0xd1 0xc7
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# CHECK: p3 = cmpb.gtu(r17, r21)
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0xa3 0xc2 0x11 0xdd
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# CHECK: p3 = cmpb.eq(r17, #21)
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0xa3 0xc2 0x31 0xdd
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# CHECK: p3 = cmpb.gt(r17, #21)
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0xa3 0xc2 0x51 0xdd
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# CHECK: p3 = cmpb.gtu(r17, #21)
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0x63 0xd5 0xd1 0xc7
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# CHECK: p3 = cmph.eq(r17, r21)
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0x83 0xd5 0xd1 0xc7
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# CHECK: p3 = cmph.gt(r17, r21)
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0xa3 0xd5 0xd1 0xc7
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# CHECK: p3 = cmph.gtu(r17, r21)
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0xab 0xc2 0x11 0xdd
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# CHECK: p3 = cmph.eq(r17, #21)
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0xab 0xc2 0x31 0xdd
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# CHECK: p3 = cmph.gt(r17, #21)
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0xab 0xc2 0x51 0xdd
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# CHECK: p3 = cmph.gtu(r17, #21)
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0x03 0xde 0x94 0xd2
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0x03 0xde 0x94 0xd2
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# CHECK: p3 = cmp.eq(r21:20, r31:30)
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# CHECK: p3 = cmp.eq(r21:20, r31:30)
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0x43 0xde 0x94 0xd2
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0x43 0xde 0x94 0xd2
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