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TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.

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llvm-svn: 28765
This commit is contained in:
Jim Laskey 2006-06-13 13:08:58 +00:00
parent 2a0f3b2e79
commit c9a71e96ae
1 changed files with 11 additions and 6 deletions
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17
lib/Target/TargetLowering.cpp
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@ -780,12 +780,14 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
case ISD::SHL:
// (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
uint64_t LowBits = (1ULL << SA->getValue())-1;
Mask >>= SA->getValue();
ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero <<= SA->getValue();
KnownOne <<= SA->getValue();
KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
KnownZero |= LowBits; // low bits known zero
KnownOne &= ~LowBits; // and known not to be one.
}
return;
case ISD::SRL:
@ -798,7 +800,8 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero >>= SA->getValue();
KnownOne >>= SA->getValue();
KnownZero |= HighBits; // high bits known zero.
KnownZero |= HighBits; // high bits known zero
KnownOne &= ~HighBits; // and known not to be one.
}
return;
case ISD::SRA:
@ -815,10 +818,12 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
if (KnownZero & SignBit) { // New bits are known zero.
KnownZero |= HighBits;
} else if (KnownOne & SignBit) { // New bits are known one.
KnownOne |= HighBits;
if (KnownZero & SignBit) {
KnownZero |= HighBits; // New bits are known zero
KnownOne &= ~HighBits; // and known not to be one.
} else if (KnownOne & SignBit) {
KnownOne |= HighBits; // New bits are known one
KnownZero &= ~HighBits; // and known not to be zero.
}
}
return;