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This is suppose to work now

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llvm-svn: 23644
This commit is contained in:
Andrew Lenharth 2005-10-06 16:54:29 +00:00
parent a3b71accf4
commit c9e3e3ee73
2 changed files with 2 additions and 1 deletions
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2
lib/Target/Alpha/AlphaISelLowering.cpp
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@ -66,6 +66,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::FREM, MVT::f64, Expand);

1
lib/Target/Alpha/AlphaISelPattern.cpp
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@ -1822,7 +1822,6 @@ void AlphaISel::Select(SDOperand N) {
} else { //ISD::TRUNCSTORE
switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
default: assert(0 && "unknown Type in store");
case MVT::i1: //FIXME: DAG does not promote this load
case MVT::i8: Opc = Alpha::STB; break;
case MVT::i16: Opc = Alpha::STW; break;
case MVT::i32: Opc = Alpha::STL; break;