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[ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate

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Differential revision: https://reviews.llvm.org/D89876
This commit is contained in:
Evgeny Leviant 2020-10-21 20:49:10 +03:00
parent b0e2ce7d07
commit c9ef46b36e
4 changed files with 4 additions and 16 deletions
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6
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -612,12 +612,6 @@ bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
return false;
}
bool ARMBaseInstrInfo::isAddrMode3OpImm(const MachineInstr &MI,
unsigned Op) const {
const MachineOperand &Offset = MI.getOperand(Op + 1);
return Offset.getReg() != 0;
}
// Load with negative register offset requires additional 1cyc and +I unit
// for Cortex A57
bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,

1
lib/Target/ARM/ARMBaseInstrInfo.h
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@ -178,7 +178,6 @@ public:
// CPSR defined in instruction
static bool isCPSRDefined(const MachineInstr &MI);
bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
// Load, scaled register offset

11
lib/Target/ARM/ARMScheduleA57.td
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@ -28,14 +28,9 @@ def IsCPSRDefinedAndPredicatedPred :
// Cortex A57 rev. r1p0 or later (false = r0px)
def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;
// If Addrmode3 contains register offset (not immediate)
def IsLdrAm3RegOffPred :
SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 1)}]>;
// The same predicate with operand offset 2 and 3:
def IsLdrAm3RegOffPredX2 :
SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 2)}]>;
def IsLdrAm3RegOffPredX3 :
SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 3)}]>;
def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;
def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;
def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;
// If Addrmode3 contains "minus register"
def IsLdrAm3NegRegOffPred :

2
test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
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@ -180,7 +180,7 @@
# CHECK-NEXT: 2 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5]
# CHECK-NEXT: 2 4 2.00 * ldrd r8, r9, [r2, #15]
# CHECK-NEXT: 4 4 2.00 * ldrd r2, r3, [r9, #32]!
# CHECK-NEXT: 4 5 2.00 * ldrd r2, r3, [r9, #32]!
# CHECK-NEXT: 4 4 2.00 * ldrd r6, r7, [r1], #8
# CHECK-NEXT: 4 4 2.00 * ldrd r2, r3, [r8], #0
# CHECK-NEXT: 4 4 2.00 * ldrd r2, r3, [r8], #0