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Use LaneBitmask::getLane in a few more places
llvm-svn: 308655
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@ -2239,7 +2239,7 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
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const MachineInstr *DefMI = nullptr;
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if (VNI->isPHIDef()) {
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// Conservatively assume that all lanes in a PHI are valid.
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LaneBitmask Lanes = SubRangeJoin ? LaneBitmask(1)
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LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0)
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: TRI->getSubRegIndexLaneMask(SubIdx);
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V.ValidLanes = V.WriteLanes = Lanes;
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} else {
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@ -2247,7 +2247,7 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
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assert(DefMI != nullptr);
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if (SubRangeJoin) {
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// We don't care about the lanes when joining subregister ranges.
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V.WriteLanes = V.ValidLanes = LaneBitmask(1);
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V.WriteLanes = V.ValidLanes = LaneBitmask::getLane(0);
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if (DefMI->isImplicitDef()) {
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V.ValidLanes = LaneBitmask::getNone();
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V.ErasableImplicitDef = true;
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@ -201,7 +201,7 @@ static LaneBitmask getUsedRegMask(const MachineOperand &MO,
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return MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(SubReg);
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auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
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if (MaxMask.getAsInteger() == 1) // cannot have subregs
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if (MaxMask == LaneBitmask::getLane(0)) // cannot have subregs
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return MaxMask;
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// For a tentative schedule LIS isn't updated yet but livemask should remain
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