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NEON VLD4(multiple 4 element structures) assembly parsing.
llvm-svn: 148762
This commit is contained in:
Jim Grosbach
parent
345c1df4df
commit
ca32a49eb5
@ -133,6 +133,15 @@ def VecListThreeQAsmOperand : AsmOperandClass {
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def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
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let ParserMatchClass = VecListThreeQAsmOperand;
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}
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// Register list of three D registers spaced by 2 (three Q registers).
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def VecListFourQAsmOperand : AsmOperandClass {
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let Name = "VecListFourQ";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
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let ParserMatchClass = VecListFourQAsmOperand;
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}
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// Register list of one D register, with "all lanes" subscripting.
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def VecListOneDAllLanesAsmOperand : AsmOperandClass {
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@ -6196,6 +6205,65 @@ def VST3qWB_register_Asm_32 :
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// VLD4 multiple structure pseudo-instructions. These need special handling for
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// the vector operands that the normal instructions don't yet model.
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// FIXME: Remove these when the register classes and instructions are updated.
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def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD4dWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VLD4dWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VLD4dWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
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(ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
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def VLD4qWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD4qWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD4qWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
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(ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
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def VLD4dWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
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(ins VecListFourD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4dWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4dWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourD:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4qWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
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(ins VecListFourQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4qWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4qWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VMOV takes an optional datatype suffix
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defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
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(VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
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@ -5317,6 +5317,26 @@ static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
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case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
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case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
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case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
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// VLD4
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case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
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case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
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case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
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case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
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case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
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case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
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case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
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case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
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case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
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case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
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case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
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case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
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case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
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case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
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case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
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case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
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case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
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case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
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}
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}
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@ -5848,6 +5868,83 @@ processInstruction(MCInst &Inst,
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return true;
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}
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// VLD4 multiple 3-element structure instructions.
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case ARM::VLD4dAsm_8:
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case ARM::VLD4dAsm_16:
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case ARM::VLD4dAsm_32:
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case ARM::VLD4qAsm_8:
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case ARM::VLD4qAsm_16:
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case ARM::VLD4qAsm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD4dWB_fixed_Asm_8:
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case ARM::VLD4dWB_fixed_Asm_16:
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case ARM::VLD4dWB_fixed_Asm_32:
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case ARM::VLD4qWB_fixed_Asm_8:
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case ARM::VLD4qWB_fixed_Asm_16:
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case ARM::VLD4qWB_fixed_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD4dWB_register_Asm_8:
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case ARM::VLD4dWB_register_Asm_16:
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case ARM::VLD4dWB_register_Asm_32:
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case ARM::VLD4qWB_register_Asm_8:
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case ARM::VLD4qWB_register_Asm_16:
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case ARM::VLD4qWB_register_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // Rm
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// VST3 multiple 3-element structure instructions.
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case ARM::VST3dAsm_8:
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case ARM::VST3dAsm_16:
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@ -1096,3 +1096,15 @@ void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
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}
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void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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// addition to get the next register, but for VFP registers, the
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// sort order is guaranteed because they're all of the form D<n>.
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O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";
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}
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@ -145,6 +145,8 @@ public:
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raw_ostream &O);
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void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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};
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} // end namespace llvm
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@ -196,25 +196,45 @@
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@ CHECK: vld3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x24,0xf4]
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@ vld4.8 {d16, d17, d18, d19}, [r0, :64]
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@ vld4.16 {d16, d17, d18, d19}, [r0, :128]
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@ vld4.32 {d16, d17, d18, d19}, [r0, :256]
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@ vld4.8 {d16, d18, d20, d22}, [r0, :256]!
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@ vld4.8 {d17, d19, d21, d23}, [r0, :256]!
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@ vld4.16 {d16, d18, d20, d22}, [r0]!
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@ vld4.16 {d17, d19, d21, d23}, [r0]!
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@ vld4.32 {d16, d18, d20, d22}, [r0]!
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@ vld4.32 {d17, d19, d21, d23}, [r0]!
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vld4.8 {d16, d17, d18, d19}, [r1, :64]
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vld4.16 {d16, d17, d18, d19}, [r2, :128]
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vld4.32 {d16, d17, d18, d19}, [r3, :256]
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vld4.8 {d17, d19, d21, d23}, [r5, :256]
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vld4.16 {d17, d19, d21, d23}, [r7]
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vld4.32 {d16, d18, d20, d22}, [r8]
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@ FIXME: vld4.8 {d16, d17, d18, d19}, [r0, :64]@ encoding: [0x1f,0x00,0x60,0xf4]
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@ FIXME: vld4.16 {d16, d17, d18, d19}, [r0,:128]@ encoding:[0x6f,0x00,0x60,0xf4]
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@ FIXME: vld4.32 {d16, d17, d18, d19}, [r0,:256]@ encoding:[0xbf,0x00,0x60,0xf4]
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@ FIXME: vld4.8 {d16, d18, d20, d22}, [r0,:256]!@ encoding:[0x3d,0x01,0x60,0xf4]
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@ FIXME: vld4.8 {d17, d19, d21, d23}, [r0,:256]!@ encoding:[0x3d,0x11,0x60,0xf4]
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@ FIXME: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4]
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@ FIXME: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4]
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@ FIXME: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4]
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@ FIXME: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4]
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vld4.s8 {d16, d17, d18, d19}, [r1, :64]!
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vld4.s16 {d16, d17, d18, d19}, [r2, :128]!
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vld4.s32 {d16, d17, d18, d19}, [r3, :256]!
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vld4.u8 {d17, d19, d21, d23}, [r5, :256]!
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vld4.u16 {d17, d19, d21, d23}, [r7]!
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vld4.u32 {d16, d18, d20, d22}, [r8]!
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vld4.p8 {d16, d17, d18, d19}, [r1, :64], r8
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vld4.p16 {d16, d17, d18, d19}, [r2], r7
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vld4.f32 {d16, d17, d18, d19}, [r3, :64], r5
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vld4.i8 {d16, d18, d20, d22}, [r4, :256], r2
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vld4.i16 {d16, d18, d20, d22}, [r6], r3
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vld4.i32 {d17, d19, d21, d23}, [r9], r4
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@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x61,0xf4]
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@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x62,0xf4]
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@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x63,0xf4]
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@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x65,0xf4]
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@ CHECK: vld4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x67,0xf4]
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@ CHECK: vld4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x68,0xf4]
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@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x61,0xf4]
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@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x62,0xf4]
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@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x63,0xf4]
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@ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x65,0xf4]
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@ CHECK: vld4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x67,0xf4]
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@ CHECK: vld4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x68,0xf4]
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@ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x61,0xf4]
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@ CHECK: vld4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x62,0xf4]
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@ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x63,0xf4]
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@ CHECK: vld4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x64,0xf4]
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@ CHECK: vld4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x66,0xf4]
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||||
@ CHECK: vld4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x69,0xf4]
|
||||
|
||||
|
||||
vld1.8 {d4[]}, [r1]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user