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Revert "[InstCombine] Optimize redundant 'signed truncation check pattern'."
At least one buildbot was able to actually trigger that assert on the top of the function. Will investigate. This reverts commit r339610. llvm-svn: 339612
This commit is contained in:
Roman Lebedev
parent
b7895b13a7
commit
ca3dcdfa5c
@ -898,131 +898,6 @@ Value *InstCombiner::foldAndOrOfICmpsOfAndWithPow2(ICmpInst *LHS, ICmpInst *RHS,
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return nullptr;
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}
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/// General pattern:
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/// X & Y
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///
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/// Where Y is checking that all the high bits (covered by a mask 4294967168)
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/// are uniform, i.e. %arg & 4294967168 can be either 4294967168 or 0
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/// Pattern can be one of:
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/// %t = add i32 %arg, 128
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/// %r = icmp ult i32 %t, 256
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/// Or
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/// %t0 = shl i32 %arg, 24
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/// %t1 = ashr i32 %t0, 24
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/// %r = icmp eq i32 %t1, %arg
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/// Or
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/// %t0 = trunc i32 %arg to i8
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/// %t1 = sext i8 %t0 to i32
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/// %r = icmp eq i32 %t1, %arg
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/// This pattern is a signed truncation check.
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///
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/// And X is checking that some bit in that same mask is zero.
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/// I.e. can be one of:
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/// %r = icmp sgt i32 %arg, -1
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/// Or
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/// %t = and i32 %arg, 2147483648
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/// %r = icmp eq i32 %t, 0
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///
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/// Since we are checking that all the bits in that mask are the same,
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/// and a particular bit is zero, what we are really checking is that all the
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/// masked bits are zero.
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/// So this should be transformed to:
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/// %r = icmp ult i32 %arg, 128
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static Value *foldSignedTruncationCheck(ICmpInst *ICmp0, ICmpInst *ICmp1,
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Instruction &CxtI,
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InstCombiner::BuilderTy &Builder) {
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assert(ICmp0 == CxtI.getOperand(0) && ICmp1 == CxtI.getOperand(1) &&
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CxtI.getOpcode() == Instruction::And);
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// Match icmp ult (add %arg, C01), C1 (C1 == C01 << 1; powers of two)
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auto tryToMatchSignedTruncationCheck = [](ICmpInst *ICmp, Value *&X,
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APInt &SignBitMask) -> bool {
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CmpInst::Predicate Pred;
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const APInt *I01, *I1; // powers of two; I1 == I01 << 1
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if (!(match(ICmp,
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m_ICmp(Pred, m_Add(m_Value(X), m_Power2(I01)), m_Power2(I1))) &&
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Pred == ICmpInst::ICMP_ULT && I1->ugt(*I01) && I01->shl(1) == *I1))
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return false;
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// Which bit is the new sign bit as per the 'signed truncation' pattern?
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SignBitMask = *I01;
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return true;
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};
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// One icmp needs to be 'signed truncation check'.
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// We need to match this first, else we will mismatch commutative cases.
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Value *X1;
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APInt HighestBit;
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ICmpInst *OtherICmp;
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if (tryToMatchSignedTruncationCheck(ICmp1, X1, HighestBit))
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OtherICmp = ICmp0;
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else if (tryToMatchSignedTruncationCheck(ICmp0, X1, HighestBit))
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OtherICmp = ICmp1;
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else
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return nullptr;
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assert(HighestBit.isPowerOf2() && "expected to be power of two (non-zero)");
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// Try to match/decompose into: icmp eq (X & Mask), 0
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auto tryToDecompose = [](ICmpInst *ICmp, Value *&X,
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APInt &UnsetBitsMask) -> bool {
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CmpInst::Predicate Pred = ICmp->getPredicate();
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// Can it be decomposed into icmp eq (X & Mask), 0 ?
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if (llvm::decomposeBitTestICmp(ICmp->getOperand(0), ICmp->getOperand(1),
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Pred, X, UnsetBitsMask,
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/*LookThruTrunc=*/false) &&
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Pred == ICmpInst::ICMP_EQ)
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return true;
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// Is it icmp eq (X & Mask), 0 already?
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const APInt *Mask;
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if (match(ICmp, m_ICmp(Pred, m_And(m_Value(X), m_APInt(Mask)), m_Zero())) &&
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Pred == ICmpInst::ICMP_EQ) {
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UnsetBitsMask = *Mask;
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return true;
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}
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return false;
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};
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// And the other icmp needs to be decomposable into a bit test.
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Value *X0;
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APInt UnsetBitsMask;
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if (!tryToDecompose(OtherICmp, X0, UnsetBitsMask))
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return nullptr;
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assert(!UnsetBitsMask.isNullValue() && "empty mask makes no sense.");
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// Are they working on the same value?
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Value *X;
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if (X1 == X0) {
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// Ok as is.
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X = X1;
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} else if (match(X0, m_Trunc(m_Specific(X1)))) {
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UnsetBitsMask = UnsetBitsMask.zext(X1->getType()->getScalarSizeInBits());
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X = X1;
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} else
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return nullptr;
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// So which bits should be uniform as per the 'signed truncation check'?
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// (all the bits starting with (i.e. including) HighestBit)
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APInt SignBitsMask = ~(HighestBit - 1U);
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// UnsetBitsMask must have some common bits with SignBitsMask,
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if (!UnsetBitsMask.intersects(SignBitsMask))
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return nullptr;
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// Does UnsetBitsMask contain any bits outside of SignBitsMask?
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if (!UnsetBitsMask.isSubsetOf(SignBitsMask)) {
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APInt OtherHighestBit = (~UnsetBitsMask) + 1U;
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if (!OtherHighestBit.isPowerOf2())
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return nullptr;
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HighestBit = APIntOps::umin(HighestBit, OtherHighestBit);
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}
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// Else, if it does not, then all is ok as-is.
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// %r = icmp ult %X, SignBit
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return Builder.CreateICmpULT(X, ConstantInt::get(X->getType(), HighestBit),
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CxtI.getName() + ".simplified");
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}
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/// Fold (icmp)&(icmp) if possible.
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Value *InstCombiner::foldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS,
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Instruction &CxtI) {
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@ -1062,9 +937,6 @@ Value *InstCombiner::foldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS,
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if (Value *V = foldAndOrOfEqualityCmpsWithConstants(LHS, RHS, true, Builder))
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return V;
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if (Value *V = foldSignedTruncationCheck(LHS, RHS, CxtI, Builder))
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return V;
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// This only handles icmp of constants: (icmp1 A, C1) & (icmp2 B, C2).
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Value *LHS0 = LHS->getOperand(0), *RHS0 = RHS->getOperand(0);
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ConstantInt *LHSC = dyn_cast<ConstantInt>(LHS->getOperand(1));
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@ -38,8 +38,11 @@
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define i1 @positive_with_signbit(i32 %arg) {
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; CHECK-LABEL: @positive_with_signbit(
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; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
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; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
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; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
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; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
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; CHECK-NEXT: ret i1 [[T4]]
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;
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%t1 = icmp sgt i32 %arg, -1
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%t2 = add i32 %arg, 128
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@ -50,8 +53,12 @@ define i1 @positive_with_signbit(i32 %arg) {
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define i1 @positive_with_mask(i32 %arg) {
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; CHECK-LABEL: @positive_with_mask(
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; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
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; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = and i32 [[ARG:%.*]], 1107296256
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; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0
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; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
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; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
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; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[T5]]
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;
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%t1 = and i32 %arg, 1107296256
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%t2 = icmp eq i32 %t1, 0
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@ -63,8 +70,11 @@ define i1 @positive_with_mask(i32 %arg) {
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define i1 @positive_with_icmp(i32 %arg) {
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; CHECK-LABEL: @positive_with_icmp(
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; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
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; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[ARG:%.*]], 512
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
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; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
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; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
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; CHECK-NEXT: ret i1 [[T4]]
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;
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%t1 = icmp ult i32 %arg, 512
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%t2 = add i32 %arg, 128
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@ -76,8 +86,11 @@ define i1 @positive_with_icmp(i32 %arg) {
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; Still the same
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define i1 @positive_with_aggressive_icmp(i32 %arg) {
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; CHECK-LABEL: @positive_with_aggressive_icmp(
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; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
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; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[ARG:%.*]], 128
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 256
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; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 512
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; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
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; CHECK-NEXT: ret i1 [[T4]]
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;
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%t1 = icmp ult i32 %arg, 128
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%t2 = add i32 %arg, 256
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@ -94,8 +107,11 @@ define i1 @positive_with_aggressive_icmp(i32 %arg) {
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define <2 x i1> @positive_vec_splat(<2 x i32> %arg) {
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; CHECK-LABEL: @positive_vec_splat(
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; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult <2 x i32> [[ARG:%.*]], <i32 128, i32 128>
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; CHECK-NEXT: ret <2 x i1> [[T4_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[ARG:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[ARG]], <i32 128, i32 128>
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; CHECK-NEXT: [[T3:%.*]] = icmp ult <2 x i32> [[T2]], <i32 256, i32 256>
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; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
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; CHECK-NEXT: ret <2 x i1> [[T4]]
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;
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%t1 = icmp sgt <2 x i32> %arg, <i32 -1, i32 -1>
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%t2 = add <2 x i32> %arg, <i32 128, i32 128>
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@ -233,8 +249,11 @@ declare i32 @gen32()
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define i1 @commutative() {
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; CHECK-LABEL: @commutative(
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; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
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; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
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; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG]], -1
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
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; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
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; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
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; CHECK-NEXT: ret i1 [[T4]]
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;
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%arg = call i32 @gen32()
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%t1 = icmp sgt i32 %arg, -1
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@ -247,8 +266,11 @@ define i1 @commutative() {
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define i1 @commutative_with_icmp() {
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; CHECK-LABEL: @commutative_with_icmp(
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; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32()
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; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
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; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[ARG]], 512
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
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; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
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; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
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; CHECK-NEXT: ret i1 [[T4]]
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;
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%arg = call i32 @gen32()
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%t1 = icmp ult i32 %arg, 512
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@ -264,8 +286,12 @@ define i1 @commutative_with_icmp() {
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define i1 @positive_trunc_signbit(i32 %arg) {
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; CHECK-LABEL: @positive_trunc_signbit(
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; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG:%.*]], 128
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; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
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; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i8
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; CHECK-NEXT: [[T2:%.*]] = icmp sgt i8 [[T1]], -1
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; CHECK-NEXT: [[T3:%.*]] = add i32 [[ARG]], 128
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; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
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; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[T5]]
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;
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%t1 = trunc i32 %arg to i8
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%t2 = icmp sgt i8 %t1, -1
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@ -278,8 +304,11 @@ define i1 @positive_trunc_signbit(i32 %arg) {
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define i1 @positive_trunc_base(i32 %arg) {
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; CHECK-LABEL: @positive_trunc_base(
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; CHECK-NEXT: [[T1:%.*]] = trunc i32 [[ARG:%.*]] to i16
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; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i16 [[T1]], 128
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; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
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; CHECK-NEXT: [[T2:%.*]] = icmp sgt i16 [[T1]], -1
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; CHECK-NEXT: [[T3:%.*]] = add i16 [[T1]], 128
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; CHECK-NEXT: [[T4:%.*]] = icmp ult i16 [[T3]], 256
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; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[T5]]
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;
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%t1 = trunc i32 %arg to i16
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%t2 = icmp sgt i16 %t1, -1
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@ -328,8 +357,8 @@ define i1 @oneuse_with_signbit(i32 %arg) {
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
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; CHECK-NEXT: call void @use1(i1 [[T3]])
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; CHECK-NEXT: [[T4_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
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; CHECK-NEXT: ret i1 [[T4_SIMPLIFIED]]
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; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
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; CHECK-NEXT: ret i1 [[T4]]
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;
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%t1 = icmp sgt i32 %arg, -1
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call void @use1(i1 %t1)
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@ -351,8 +380,8 @@ define i1 @oneuse_with_mask(i32 %arg) {
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; CHECK-NEXT: call void @use32(i32 [[T3]])
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; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[T3]], 256
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; CHECK-NEXT: call void @use1(i1 [[T4]])
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; CHECK-NEXT: [[T5_SIMPLIFIED:%.*]] = icmp ult i32 [[ARG]], 128
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; CHECK-NEXT: ret i1 [[T5_SIMPLIFIED]]
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; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]]
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; CHECK-NEXT: ret i1 [[T5]]
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;
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%t1 = and i32 %arg, 603979776 ; some bit within the target 4294967168 mask.
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call void @use32(i32 %t1)
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